A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 12, 2010, Pages 1745-1752

  Hoya, Katsuhiko ^a   Takashima, Daisaburo ^a   Shiratake, Shinichiro ^a   Ogiwara, Ryu ^a   Miyakawa, Tadashi ^a   Shiga, Hidehiro ^a   Doumae, Sumiko M ^a   Ohtsuki, Sumito ^a   Kumura, Yoshinori ^a   Shuto, Susumu ^a   Ozaki, Tohru ^a   Yamakawa, Koji ^a   Kunishima, Iwao ^a   Nitayama, Akihiro ^a   Fujii, Shuso ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Burst mode; ferroelectric memory; nonvolatile memory

Indexed keywords

BIT LINES; BIT-LINE ARCHITECTURE; BURST MODE; CELL ARRAY; CELL SIZE; CHIP SIZES; CMOS TECHNOLOGY; COUPLING NOISE; CYCLE TIME; DIE SIZE; FERRO-ELECTRIC RAMS; FERROELECTRIC MEMORY; HIGH-SPEED; NON-VOLATILE MEMORIES; POWER CONSUMPTION; RELIABILITY IMPROVEMENT; SENSE AMPLIFIER;

CMOS INTEGRATED CIRCUITS; FERROELECTRIC DEVICES; FERROELECTRICITY;

RANDOM ACCESS STORAGE;

EID: 78649496253     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2034380     Document Type: Article

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