A non-volatile flip-flop in magnetic FPGA chip

Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

Volumn , Issue , 2006, Pages 323-326

  Zhao, W ^a   Belhaire, E ^a   Javerliac, V ^b   Chappert, C ^a   Dieny, B ^b  

^a CNRS   (France)

^b CEA GRENOBLE   (France)

Author keywords

Flip flop; High speed; Low power; Magnetic; MRAM; MTJ; Non volatile; SOC; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAGNETIC RECORDING; MAGNETIC STORAGE; MAGNETISM; MRAM DEVICES; NANOTECHNOLOGY; PROGRAMMABLE LOGIC CONTROLLERS; STATIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP; TUNNEL JUNCTIONS;

HIGH SPEED; LOW POWER; MAGNETIC; MRAM; NON-VOLATILE;

FLIP FLOP CIRCUITS;

EID: 78650315538     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dtis.2006.1708702     Document Type: Conference Paper

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