Runtime power management of 3-D multi-core architectures under peak power and temperature constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 6, 2011, Pages 905-918

  Kang, Kyungsu ^a   Kim, Jungsoo ^a   Yoo, Sungjoo ^b   Kyung, Chong Min ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

3 D integration; chip multiprocessor; dynamic voltage and frequency scaling (DVFS); power management; thermal management

Indexed keywords

3-D INTEGRATION; CHIP-MULTIPROCESSOR; DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVFS); POWER MANAGEMENT; THERMAL MANAGEMENT;

BUFFER STORAGE; DELAY CIRCUITS; ENERGY UTILIZATION; INTEGRATION; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS;

THREE DIMENSIONAL;

EID: 79957457905     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2101371     Document Type: Article

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