Three-dimensional chip-multiprocessor run-time thermal management

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 8, 2008, Pages 1479-1492

  Zhu, Changyun ^a,b   Gu, Zhenyu ^a,c   Shang, Li ^a,d   Dick, Robert P ^a,e   Joseph, Russ ^a,e  

^a IEEE

^b QUEEN S UNIVERSITY   (Canada)

^c SYNOPSYS INC   (United States)

^d UCB 450   (United States)

^e Northwestern University   (United States)

Author keywords

3 D integration; Chip multiprocessor; Thermal management

Indexed keywords

COMPUTER OPERATING SYSTEMS; ENERGY MANAGEMENT; INDUSTRIAL MANAGEMENT; MANAGEMENT; MULTIPROCESSING SYSTEMS; MULTIPROGRAMMING; NANOTECHNOLOGY; TEMPERATURE CONTROL; THERMAL VARIABLES CONTROL; THREE DIMENSIONAL;

CHIP-LEVEL; COMMUNICATION LATENCY; FULL SYSTEM SIMULATIONS; GENERAL SOLUTIONS; HIGH POWER DENSITY (HPD); INTEGRATED POWER; INTEGRATION DENSITIES; LOCAL INFORMATION; MANAGEMENT TECHNIQUES; MULTI-THREADED; OPERATING SYSTEMS; POWER CHARACTERISTICS; PROCESSOR CORES; RUN TIME; SOFTWARE COMPONENTS; SOURCE CODING; THREE DIMENSIONAL (3-D) INTEGRATION; THREE DIMENSIONAL (3D);

INFORMATION MANAGEMENT;

EID: 47849132667     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.925793     Document Type: Article

References (53)

1. R. Kalla, B. Sinharoy, and J. M. Tendler, "IBM Power5 chip: A dualcore multithreaded processor," IEEE Micro, vol. 24, no. 2, pp. 40-47, Mar./Apr. 2004.
2. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, Mar./Apr. 2005.
3. AMD Multi-Core White Paper. [Online]. Available: http://www.amd.com.
4. Intel Multi-Core Processor Architecture. [Online]. Available: http://www.intel.com.
5. M. B. Taylor et al., "Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams," in Proc. Int. Symp. Comput. Archit., Jun. 2004, pp. 2-13.
6. K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP using polymorphism in the TRIPS architecture," in Proc. Int. Symp. Comput. Archit., Jun. 2003, pp. 422-433.
7. S. Vangal et al., "An 80-tile 1.28 TFLOPS networks-on-chip in 65 nm CMOS," in Proc. Int. Solid-State Circuits Conf., Feb. 2007, pp. 98-100.
8. V. Agarwal et al., "Clock rate vs. IPC: The end of the road for conventional microarchitectures," in Proc. Int. Symp. Comput. Archit., Jun. 2000, pp. 276-283.
9. A. W. Topol et al., "Three-dimensional integrated circuits," IBM I. Res. Develop., vol. 50, no. 4/5, pp. 491-506, 2006.
10. B. Black et al., "Die stacking (3D) microarchitecture," in Proc. Int. Symp. Microarchitecture, Dec. 2006, pp. 469-479.
11. Samsung. [Online]. Available: http://www.samsung.com/
12. Tezzaron. [Online]. Available: http://www.tezzaron.com/technology/ FaStack.htm
13. F. Li et al., "Design and management of 3D chip multiprocessors using network-in-memory," in Proc. Int. Symp. Comput. Archit., Jun. 2006, pp. 130-141.
14. T. Kgil et al., "PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor," in Proc. Int. Conf. Architectural Support Program. Lang. Operating Syst., Oct. 2006, pp. 117-128.
15. J. Kim et al., "A novel dimensionally-decomposed router for on-chip communication in 3D architectures," in Proc. Int. Symp. Comput. Archit., Jun. 2007, pp. 138-149.
16. Y. Li et al., "Performance, energy, and thermal considerations for SMT and CMP architectures," in Proc. Int. Symp. Comput. Archit., Feb. 2005, pp. 71-82.
17. J. Donald and M. Martonosi, "Techniques for multicore thermal management: Classification and new exploration," in Proc. Int. Symp. Comput. Archit., Jun. 2006, pp. 78-88.
18. D. Brooks and M. Martonosi, "Dynamic thermal management for high-performance microprocessors," in Proc. Int. Symp. High-Perform. Comput. Archit., Jan. 2001, pp. 171-182.
19. K. Skadron et al., "Temperature-aware microarchitecture, " in Proc. Int. Symp. Comput. Archit., Jun. 2003, pp. 2-13.
20. K. Puttaswamy and G. H. Loh, "Thermal analysis of a 3D die-stacked high-performance microprocessor," in Proc. Great Lakes Symp. VLSI, May 2006, pp. 19-24.
21. K. Puttaswamy and G. H. Loh, "Thermal herding: Microarchitecture techniques for controlling hotspots in high-performance 3D-integratedprocessors, " in Proc. Int. Symp. High-Perform. Comput. Archit., Feb. 2007, pp. 193-204.
22. G. M. Link and N. Vijaykrishnan, "Thermal trends in emerging technologies," in Proc. Int. Symp. Quality Electron. Des., Mar. 2006, pp. 625-632.
23. M. D. Powell, M. Gomaa, and T. N. Vijaykumar, "Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system," in Proc. Int. Conf. Architectural Support Program. Lang. Operating Syst., Nov. 2004, pp. 260-270.
24. J. McGregor, "x86 power and thermal management," Microprocess. Rep., vol. 18, no. 12, pp. 1-8, Dec. 2004.
25. A. Mallik et al., "HCSEL: Measuring user-perceived performance to control dynamic frequency scaling," in Proc. Int. Conf. Architectural Support Program. Lang. Operating Syst., Mar. 2008, pp. 70-79.
26. N. L. Binkert et al., "The M5 simulator: Modeling networked systems," in Proc. Int. Symp. Microarchitecture, 2006, vol. 26, pp. 52-60. no. 4.
27. M. Healy et al., "Multi-objective microarchitectural floorplanning for 2D and 3D ICS," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 1, pp. 38-52, Jan. 2007.
28. Y Tsai et al., "Three-dimensional cache design exploration using 3DCacti," in Proc. Int. Conf. Comput. Des., Oct. 2005, pp. 519-524.
29. G. L. Loi et al., "A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy," in Proc. Des. Autom. Conf., Jul. 2006, pp. 991-996.
30. Y. Li et al., "CMP design space exploration subject to physical constraints," in Proc. Int. Symp. High-Perform. Comput. Archit., Feb. 2006, pp. 17-28.
31. C. Sun, L. Shang, and R. P. Dick, "Three-dimensional multi-processor system-on-chip thermal optimization," in Proc. Int. Conf. Hardware/Software Codes. Syst. Synth., Oct. 2007, pp. 117-122.
32. S. Heo, K. Barr, and K. Asanovic, "Reducing power density through activity migration," in Proc. Int. Symp. Low Power Electmn. Des., Aug. 2003, pp. 217-222.
33. A. Kumar et al., "HybDTM: A coordinated hardware-software approach for dynamic thermal management," in Pmc. Des. Autom. Conf, Jul. 2006, pp. 548-553.
34. S. Park et al., "Managing energy-performance tradeoffs for multi-threaded applications," in Proc. Int. Conf. Meas. Modeling Comput. Syst., Jun. 2007, pp. 169-180.
35. COMSOL Multiphysics, COMSOL, Inc. [Online]. Available: http://www.co.msol.com/products/multiphys.ics
36. ANSYS. [Online]. Available: http://www.ansys.com.
37. Y. Yang et al., "Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2006, pp. 575-582.
38. U. Miekkala, "Graph properties for splitting with grounded Laplacian matrices," BIT Numer. Math., vol. 33, no. 3, pp. 485-495, Sep. 1993.
39. Y.-K. Cheng et al., Electrothermal Analysis of VLSI Systems. Cambridge, U.K.: Cambridge Univ. Press, 2000.
40. Y. Zhang et al., "HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects," Univ. Virginia, Charlottesville, VA, Tech. Rep. CS-2003-05, May 2003.
41. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Pmc. Int. Symp. Comput. Archit., Jun. 2000, pp. 83-94.
42. K. A. Bowman et al., "A physical alpha-power law MOSFET model," IEEE I. Solid-State Circuits, vol. 34, no. 10, pp. 1410-1414, Oct. 1999.
43. D. Pham. et al., "The design and implementation of a first-generation CELL processor," in Proc. Int. Solid-State Circuits Conf., Feb. 2007, pp. 49-52.
44. R. Sprunt, "Pentium 4 performance-monitoring features," IEEE Micro, vol. 22, no. 4, pp. 72-82, Jul./Aug. 2002.
45. C. Isci and M. Martonosi, "Runtime power monitoring in high-end processors: Methodology and empirical data," in Proc. Int. Symp. Micmarchitecture, Dec. 2003, pp. 93-104.
46. C. Isci et al., "An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget," in Proc. Int. Symp. Microarchitecture, Dec. 2006, pp. 347-358.
47. D. Tarjan, S. Thoziyoor, and N. P. Jouppi, "CACTI 4.0," HP Laboratories, Palo Alto, CA, Tech. Rep. HPL-2006-86, Jun. 2006.
48. J. Srinivasan et al., "Exploiting structural duplication for lifetime reliability enhancement," in Proc. Int. Symp. Comput. Archit., Jun. 2005, pp. 520-531.
49. E. C Samson et al., "Interface material selection and a thermal management technique in second-generation platforms built on Intel Centrino mobile technology," Intel Technol. I., vol. 9, no. 1, pp. 75-86, Feb. 2005.
50. R. Viswanath et al., "Thermal performance challenges from silicon to systems," Intel Technol. J., vol. 4, no. 3, pp. 1-16, Aug. 2000.
51. M.-L. Li et al., "The ALPBench benchmark suite for complex multimedia applications," in Proc. Int. Symp. Workload Characterization, Oct. 2005, pp. 34-35.
52. SPLASH2 Website. [Online]. Available: http://www-flash.stanford. edu/apps/SPLASH/
53. A. Phansalkar et al., "Measuring program similarity: Experiments with SPEC CPU benchmark suites," in Proc. Int. Symp. Perform. Anal. Syst. Software, Mar. 2005, pp. 10-20.