IBM POWER6 microarchitecture

IBM Journal of Research and Development

Volumn 51, Issue 6, 2007, Pages 639-662

  Le, Hung Q ^a   Starke, William J ^a   Fields, J Stephen ^a   O'Connell, Francis P ^a   Nguyen, Dung Q ^a   Ronchetti, Bruce J ^a   Sauer, Wolfram M ^a   Schwarz, Eric M ^a   Vaden, Michael T ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; MULTIPROCESSING SYSTEMS; SCALABILITY;

BINARY COMPATIBILITY; DECIMAL FLOATING-POINT; SIMULTANEOUS MULTITHREADED DUAL-CORE CHIP; SYMMETRIC MULTIPROCESSING; VECTOR MULTIMEDIA EXTENSION;

SOFTWARE ARCHITECTURE;

EID: 37549032725     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0639     Document Type: Article

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