-
2
-
-
0032592096
-
Design challenges of technology scaling
-
Jul.-Aug.
-
S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul.-Aug. 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.4
, pp. 23-29
-
-
Borkar, S.1
-
5
-
-
27844438093
-
Changing vectors of moore's law-keynote speech
-
San Francisco, CA, Dec.
-
A. S. Grove, "Changing vectors of Moore's law-Keynote Speech," presented at the Int. Electron Devices Meeting, San Francisco, CA, Dec. 2002.
-
(2002)
Int. Electron Devices Meeting
-
-
Grove, A.S.1
-
8
-
-
0033712191
-
The design and use of simplepower: A cycle-accurate energy estimation tool
-
Anaheim, CA, Jun.
-
W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of simplepower: a cycle-accurate energy estimation tool," presented at the Design Automation Conf. (DAC), Anaheim, CA, Jun. 2000.
-
(2000)
Design Automation Conf. (DAC)
-
-
Ye, W.1
Vijaykrishnan, N.2
Kandemir, M.3
Irwin, M.J.4
-
9
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis optimization
-
Vancouver, BC, Canada, Jun.
-
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis optimization," presented at the 27th Annu. Int. Symp. Computer Architecture (ISCA), Vancouver, BC, Canada, Jun. 2000.
-
(2000)
27th Annu. Int. Symp. Computer Architecture (ISCA)
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
10
-
-
0036911590
-
Leakage power modeling and reduction with data retention
-
San Jose, CA, Nov.
-
W. Liao, J. M. Basile, and L. He, "Leakage power modeling and reduction with data retention," presented at the Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2002.
-
(2002)
The Int. Conf. Computer-aided Design (ICCAD)
-
-
Liao, W.1
Basile, J.M.2
He, L.3
-
11
-
-
0031623626
-
Estimation of standby leakage power in cmos circuits considering accurate modeling of transistor stacks
-
Monterey, CA, Aug.
-
Z. Cheng, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in cmos circuits considering accurate modeling of transistor stacks," presented at the Int. Symp. Low Power Electronics and Design (ISLPED), Monterey, CA, Aug. 1998.
-
(1998)
Int. Symp. Low Power Electronics and Design (ISLPED)
-
-
Cheng, Z.1
Johnson, M.2
Wei, L.3
Roy, K.4
-
12
-
-
2942747775
-
A static power model for architects
-
Monterey, CA, Dec.
-
J. Butts and G. Sohi, "A static power model for architects," presented at the MICRO-33, Monterey, CA, Dec. 2000.
-
(2000)
MICRO-33
-
-
Butts, J.1
Sohi, G.2
-
13
-
-
84962324887
-
Topological analysis for leakage prediction on digital circuits
-
Bangalore, India, Jan.
-
W. Jiang, V. Tiwari, E. de la Iglesia, and A. Sinha, "Topological analysis for leakage prediction on digital circuits," presented at the Joint 7th Asia and South Pacific Design Automation Conf. and 15th Int. Conf. VLSI Design, Bangalore, India, Jan. 2002.
-
(2002)
Joint 7th Asia and South Pacific Design Automation Conf. and 15th Int. Conf. VLSI Design
-
-
Jiang, W.1
Tiwari, V.2
De La Iglesia, E.3
Sinha, A.4
-
14
-
-
0036949325
-
Full-chip subthreshold leakage power prediction model for sub-0.18 μm cmos
-
Monterey, CA, Aug.
-
S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip subthreshold leakage power prediction model for sub-0.18 μm cmos," presented at the Int. Symp. Low Power Electronics and Design (ISLPED), Monterey, CA, Aug. 2002.
-
(2002)
Int. Symp. Low Power Electronics and Design (ISLPED)
-
-
Narendra, S.1
De, V.2
Borkar, S.3
Antoniadis, D.4
Chandrakasan, A.5
-
17
-
-
1542359151
-
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
-
Seoul, Korea, Aug.
-
W. Liao, F. Li, and L. He, "Microarchitecture level power and thermal simulation considering temperature dependent leakage model," presented at the Int. Symp. Low Power Electronics and Design (ISLPED), Seoul, Korea, Aug. 2003.
-
(2003)
Int. Symp. Low Power Electronics and Design (ISLPED)
-
-
Li, F.1
He, L.2
-
18
-
-
1142270611
-
Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management
-
Boston, MA, Feb.
-
K. Skadron, T. Abdelzaher, and M. Stan, "Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management," presented at the 8th Int. Symp. High-Performance Computer Architecture (HPCA), Boston, MA, Feb. 2002.
-
(2002)
8th Int. Symp. High-performance Computer Architecture (HPCA)
-
-
Skadron, K.1
Abdelzaher, T.2
Stan, M.3
-
19
-
-
0038684860
-
Temperature-aware microarchitecture
-
San Diego, CA, Jun.
-
K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," presented at the 30th Int. Symp. Computer Architecture, San Diego, CA, Jun. 2003.
-
(2003)
30th Int. Symp. Computer Architecture
-
-
Skadron, K.1
Stan, M.2
Huang, W.3
Velusamy, S.4
Sankaranarayanan, K.5
Tarjan, D.6
-
20
-
-
1542269347
-
Reducing power density through activity migration
-
Seoul, Korea, Aug.
-
S. Heo, K. Barr, and K. Asanovic, "Reducing power density through activity migration," presented at the Int. Symp. Low Power Electronics and Design (ISLPED), Seoul, Korea, Aug. 2003.
-
(2003)
Int. Symp. Low Power Electronics and Design (ISLPED)
-
-
Heo, S.1
Barr, K.2
Asanovic, K.3
-
21
-
-
34249306904
-
Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects
-
Dept. Comput. Sci., Univ. Virginia, Charlottesville, VA, Mar.
-
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, "Hotleakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects," Dept. Comput. Sci., Univ. Virginia, Charlottesville, VA, Tech. Rep. CS-2003-05, Mar. 2003.
-
(2003)
Tech. Rep.
, vol.CS-2003-05
-
-
Zhang, Y.1
Parikh, D.2
Sankaranarayanan, K.3
Skadron, K.4
Stan, M.5
-
22
-
-
22544479188
-
-
[Online]
-
PTscalar (2004). [Online]. Available: http://eda.ee.ucla.edu/PTscalar/
-
(2004)
-
-
-
23
-
-
0029359285
-
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
-
Aug.
-
S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, Issue.8
, pp. 847-854
-
-
Mutoh, S.1
-
24
-
-
0041589378
-
Analysis and minimization techniques for total leakage considering gate oxide leakage
-
New Orleans, LA, Jun.
-
D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and minimization techniques for total leakage considering gate oxide leakage," presented at the Design Automation Conf. (DAC), New Orleans, LA, Jun. 2003.
-
(2003)
Design Automation Conf. (DAC)
-
-
Lee, D.1
Kwong, W.2
Blaauw, D.3
Sylvester, D.4
-
25
-
-
22544453934
-
High level area and current estimation
-
Yokohama, Japan, Jan.
-
F. Li, L. He, J. Basile, R. J. Patel, and H. Ramamurthy, "High level area and current estimation," presented at the Asia and South Pacific Design Automation Conf., Yokohama, Japan, Jan. 2004.
-
(2004)
Asia and South Pacific Design Automation Conf.
-
-
Li, F.1
He, L.2
Basile, J.3
Patel, R.J.4
Ramamurthy, H.5
-
26
-
-
0003647211
-
-
MCNC, Research Triangle Park, NC, Jan.
-
S. Yang, "Logic synthesis and optimization benchmarks user guide-ver, 3.0," MCNC, Research Triangle Park, NC, Jan. 1991.
-
(1991)
Logic Synthesis and Optimization Benchmarks User Guide-ver, 3.0
-
-
Yang, S.1
-
27
-
-
22544483285
-
-
Univ. California, Berkeley, CA, Jul.
-
UC Berkeley Device Group, "BSIM 4 MOSFET Model," Univ. California, Berkeley, CA, Jul. 2002.
-
(2002)
BSIM 4 MOSFET Model
-
-
-
28
-
-
14244267091
-
-
Univ. California, Berkeley, CA, Jul.
-
UC Berkeley Device Group, "Berkeley Predictive Technology Model (BPTM)," Univ. California, Berkeley, CA, Jul. 2002.
-
(2002)
Berkeley Predictive Technology Model (BPTM)
-
-
-
29
-
-
85013303687
-
Temperature effects on MOS transistors
-
R. Cobbold, "Temperature effects on MOS transistors," Electron. Lett., vol. 2, pp. 190-192, 1966.
-
(1966)
Electron. Lett.
, vol.2
, pp. 190-192
-
-
Cobbold, R.1
-
31
-
-
2342635671
-
Cacti 3.0: An integrated cache timing, power, and area model
-
P. Shivakumar and N. P. Jouppi, "Cacti 3.0: An Integrated Cache Timing, Power, and Area Model," WRL, Research Rep. 2001/2, 2001.
-
(2001)
WRL, Research Rep.
, vol.2001
, Issue.2
-
-
Shivakumar, P.1
Jouppi, N.P.2
-
32
-
-
0031069405
-
A 600 MHz superscalar RISC microprocessor with out-of-order execution
-
B. A. Gieseke et al., "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1997, pp. 176-177.
-
(1997)
IEEE Int. Solid-state Circuits Conf. Dig. Tech. Papers
, pp. 176-177
-
-
Gieseke, B.A.1
-
33
-
-
0003926726
-
Quantifying the complexity of superscalar processors
-
Univ. Wisconsin-Madison, Nov.
-
N. S. Palacharla and J. E. Smith, "Quantifying the complexity of superscalar processors," Univ. Wisconsin-Madison, Technology Rep. CSTR-96-1328, Nov. 1996.
-
(1996)
Technology Rep.
, vol.CSTR-96-1328
-
-
Palacharla, N.S.1
Smith, J.E.2
-
35
-
-
22544435266
-
-
Siliconix, Santa Clara, CA, Siliconix Application Note AN83-10, Nov.
-
R. Severns, "Safe operating area and thermal design for MOSPOWER transistors," Siliconix, Santa Clara, CA, Siliconix Application Note AN83-10, Nov. 1983.
-
(1983)
Safe Operating Area and Thermal Design for MOSPOWER Transistors
-
-
Severns, R.1
-
36
-
-
0031639693
-
Reducing power in high-performance microprocessors
-
San Francisco, CA, Jun.
-
V. Tiwari, D. Singh, S. Rajgopal, and O. Mehta, "Reducing power in high-performance microprocessors," presented at the Design Automation Conf. (DAC), San Francisco, CA, Jun. 1998.
-
(1998)
Design Automation Conf. (DAC)
-
-
Tiwari, V.1
Singh, D.2
Rajgopal, S.3
Mehta, O.4
-
38
-
-
0036458032
-
Enhanced thermal management by direct water spray of high-voltage, high power devices in a three-phase, 18-hp ac motor drive demonstration
-
San Diego, CA, Jun.
-
M. Shaw, J. Waldrop, S. Chandrasekaran, B. Kagalwala, X. Jing, E. Brown, V. Dhir, and M. Fabbeo, "Enhanced thermal management by direct water spray of high-voltage, high power devices in a three-phase, 18-hp ac motor drive demonstration," presented at the 8th Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm'02), San Diego, CA, Jun. 2002.
-
(2002)
8th Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm'02)
-
-
Shaw, M.1
Waldrop, J.2
Chandrasekaran, S.3
Kagalwala, B.4
Jing, X.5
Brown, E.6
Dhir, V.7
Fabbeo, M.8
-
39
-
-
0032122783
-
Impact of self-heating and thermal coupling on analog circuits in SOI CMOS
-
Jul.
-
B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan, and M. J. Uren, "Impact of self-heating and thermal coupling on analog circuits in SOI CMOS," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1037-1046, Jul. 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, Issue.7
, pp. 1037-1046
-
-
Tenbroek, B.M.1
Lee, M.S.L.2
Redman-White, W.3
Bunyan, R.J.T.4
Uren, M.J.5
|