UltraSPARC T2: A highly-threaded, power-efficient, SPARC SOC

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 22-25

  Shah, Manish ^a   Barreh, Jama ^a   Brooks, Jeff ^a   Golla, Robert ^a   Grohoski, Gregory ^a   Gura, Nils ^a   Hetherington, Rick ^a   Jordan, Paul ^a   Luttrell, Mark ^a   Olson, Christopher ^a   Saha, Bikram ^a   Sheahan, Denis ^a   Spracklen, Lawrence ^a   Wynn, Aaron ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDPASS FILTERS; COMPUTER NETWORKS; INTEGRATED CIRCUITS; INTERFACES (COMPUTER); THROUGHPUT;

ULTRASPARC;

MICROPROCESSOR CHIPS;

EID: 51349168284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425786     Document Type: Conference Paper

References (5)

1. J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach, Fourth Edition, Morgan Kaufmann, San Francisco, CA. 2007.
2. G. Grohoski, "Niagara-2: A Highly Threaded Server-on-a-Chip," 18th Hot Chips Symposium, Aug., 2006.
3. U. G. Nawathe, et al., "An 8-Core 64 Thread 64b Power-Efficient SPARC SoC," in IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech Papers, Feb. 2007, pp. 108-110.
4. A. S. Leon, et al., "A Power-Efficient High Throughput 32-Thread SPARC Processor," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech Papers, Feb. 2006, pp. 98-99.
5. Samuel Williams, Leonid Oliker, Richard Vuduc, John Shalf, Katherine Yelick, James Demmel "Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms," unpublished.