The implementation of the 65nm dual-core 64b merom processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 106-108

  Sakran, Nabeel ^a   Yuffe, Marcelo ^a   Mehalel, Moty ^a   Doweck, Jack ^a   Knoll, Ernest ^a   Kovacs, Avi ^a  

^a INTEL CORPORATION   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; NATURAL FREQUENCIES; PROGRAM PROCESSORS;

BUS FREQUENCY RANGE; MEROM PROCESSORS; POWER PERFORMANCE;

MICROPROCESSOR CHIPS;

EID: 34548817260     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373610     Document Type: Conference Paper

References (2)

1. 2 SRAM Cell," IEDM Tech. Dig., pp. 657-660, Dec., 2004.
2. S. Rusu, S. Tam, H. Muljono, et al., "A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache," ISSCC Tech. Digest, pp. 118-119, Feb., 2006.