Obstacle-aware clock-tree shaping during placement

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2011, Pages 123-130

  Lee, Dong Jin ^a   Markov, Igor L ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

clock network; clock tree; low power; placement

Indexed keywords

CLOCK NETWORK; CLOCK NETWORK SYNTHESIS; CLOCK ROUTING; CLOCK TREE; CLOCK-TREE SYNTHESIS; CONTRACTION FORCE; CONVENTIONAL APPROACH; DYNAMIC POWER CONSUMPTION; GATED CLOCKS; IC DESIGNS; LARGE SIZES; LOW POWER; MACRO BLOCK; MULTIPLE CLOCK DOMAINS; NETWORK SYNTHESIS; OBSTACLE AVOIDANCE; PLACEMENT; RECENT PROGRESS; SOFTWARE IMPLEMENTATION; TREE BRANCHES;

DESIGN; OPTIMIZATION;

ELECTRIC CLOCKS;

EID: 79955062779     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1960397.1960425     Document Type: Conference Paper

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