CEP: A clock-driven ECO placement algorithm for standard-cell layout

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 118-121

  Liu, Yi ^a   Hong, Xianlong ^a   Cai, Yici ^a   Wu, Weimin ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; FLIP FLOP CIRCUITS; OPTIMIZATION; VLSI CIRCUITS;

CLOCK ROUTING; ENGINEER CHANGE ORDER; PLACEMENT ALGORITHM; SYNCHRONOUS CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035719251     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (7)

1. Zero skew clock routing with minimum wirelength
2. On the bounded-skew clock and steiner routing problems
3. Buffer insertion and sizing under process variations for low power clock distribution
4. Useful-skew clock routing with gate sizing for low power design
5. Clock-skew constrained cell placement
6. Incremental layout placement modification algorithms
7. Buffered clock tree synthesis with non-zero clock skew scheduling for increased tolerance to process parameter variations