Gated clock routing for low-power microprocessor design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 6, 2001, Pages 715-722

  Oh, Jaewon ^a   Pedram, Massoud ^b,c  

^a SUN MICROSYSTEMS   (United States)

^b IEEE

^c University of Southern California ^*  (United States)

Author keywords

Clock routing; Gated clock; Low power; VLSI

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DYNAMIC PROGRAMMING; HEURISTIC METHODS; LOGIC GATES; MICROPROCESSOR CHIPS; TIMING CIRCUITS; VLSI CIRCUITS;

GATE REDUCTION HEURISTIC; ZERO SKEW GATED CLOCK ROUTING TECHNIQUE;

SWITCHING THEORY;

EID: 0035368814     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.924825     Document Type: Article

References (7)

1. Automatic synthesis of low-power gated-clock finite-state machines
2. Zero-skew clock routing trees with minimum wirelength
3. Minimum path-length equi-distance routing
4. Power reduction in microprocessor chips by gated clock routing
5. Gated clock routing minimizing the switched capacitance
6. Activity driven clock design for low power circuits
7. Exact zero skew