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Volumn , Issue , 2010, Pages 1468-1473

Contango: Integrated optimization of SoC clock networks

Author keywords

[No Author keywords available]

Indexed keywords

ADVERSE EFFECT; CLOCK NETWORK; CONTANGO; INTEGRATED OPTIMIZATION; ON-CHIP CLOCKS; SEMICONDUCTOR TECHNOLOGY; SYNCHRONOUS CIRCUITS; TEXAS INSTRUMENTS;

EID: 77953087445     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (15)
  • 1
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    • Zero-Skew Clock Routing Trees with Minimum Wirelength
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  • 2
    • 0026946698 scopus 로고
    • Zero Skew Clock Routing with Minimum Wirelength
    • T.-H. Chao et al., "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. on Circ. & Sys., 39(11), pp. 799-814, 1992.
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  • 3
    • 22644449767 scopus 로고    scopus 로고
    • Bounded-Skew Clock and Steiner Routing
    • J. Cong et al, "Bounded-Skew Clock and Steiner Routing," ACM Trans. on DAES 1998, pp. 341-388.
    • (1998) ACM Trans. on DAES , pp. 341-388
    • Cong, J.1
  • 4
    • 0027262847 scopus 로고    scopus 로고
    • A Clustering-Based Optimization Algorithm in Zero-Skew Routings
    • M. Edahiro, "A Clustering-Based Optimization Algorithm in Zero-Skew Routings," DAC'93, pp. 612-616.
    • DAC'93 , pp. 612-616
    • Edahiro, M.1
  • 5
    • 0025594311 scopus 로고    scopus 로고
    • Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay
    • L. v. Ginneken, "Buffer Placement in Distributed RC-tree Networks For Minimal Elmore Delay," ISCAS'90,pp.865-868.
    • ISCAS'90 , pp. 865-868
    • Ginneken, L.V.1
  • 6
    • 33646922057 scopus 로고    scopus 로고
    • The Future of Wires
    • R. Ho, K. Mai, M. Horowitz, "The Future of Wires," Proc. IEEE, 89(4), pp. 490-504, 2001.
    • (2001) Proc. IEEE , vol.89 , Issue.4 , pp. 490-504
    • Ho, R.1    Mai, K.2    Horowitz, M.3
  • 7
    • 77953095761 scopus 로고    scopus 로고
    • On Bounded-Skew Routing Tree Problem
    • J.-H. Huang, A. B. Kahng, C.-W. Tsao, "On Bounded-Skew Routing Tree Problem," DAC'95, pp.508-513.
    • DAC'95 , pp. 508-513
    • Huang, J.-H.1    Kahng, A.B.2    Tsao, C.-W.3
  • 8
    • 0031163197 scopus 로고    scopus 로고
    • Practical Bounded-Skew Clock Routing
    • A. B. Kahng,C.-W. Tsao,"Practical Bounded-Skew Clock Routing," J. VLSI Signal Proc. 16(1997), pp.199-215.
    • (1997) J. VLSI Signal Proc. , vol.16 , pp. 199-215
    • Kahng, A.B.1    Tsao, C.-W.2
  • 9
    • 84893765568 scopus 로고    scopus 로고
    • Interconnect Tuning Strategies for High-Performance ICs
    • A. B. Kahng et al, "Interconnect Tuning Strategies for High-Performance ICs," DATE'98, pp. 471-478.
    • DATE'98 , pp. 471-478
    • Kahng, A.B.1
  • 10
    • 43349093078 scopus 로고    scopus 로고
    • An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction
    • J. Long, H. Zhou, S.O. Memik, "An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction," ISPD'08, pp. 126-133.
    • ISPD'08 , pp. 126-133
    • Long, J.1    Zhou, H.2    Memik, S.O.3
  • 11
    • 70349150933 scopus 로고    scopus 로고
    • An Algorithm for Routing with Capacitance/Distance Constraints for Clock Distribution in Microprocessors
    • R. S. Shelar, "An Algorithm for Routing with Capacitance/Distance Constraints for Clock Distribution in Microprocessors," ISPD'09, pp. 141-148.
    • ISPD'09 , pp. 141-148
    • Shelar, R.S.1
  • 12
    • 20444462290 scopus 로고    scopus 로고
    • A Fast Algorithm for Optimal Buffer Insertion
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    • Shi, W.1    Li, Z.2
  • 13
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    • ISPD 2009 Clock-network Synthesis Contest
    • C. Sze et al, "ISPD 2009 Clock-network Synthesis Contest," ISPD'09, pp. 149-150. http://www.sigda.org/ispd/contests/ispd09cts.html.
    • ISPD'09 , pp. 149-150
    • Sze, C.1
  • 14
    • 0027544071 scopus 로고
    • An Exact Zero-Skew Clock Routing Algorithm
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  • 15
    • 33750600861 scopus 로고    scopus 로고
    • New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
    • W. Zhao, Y. Cao, "New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration," IEEE Trans. on Electron Devices, 53(11), pp. 2816-2823, 2006.
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    • Zhao, W.1    Cao, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.