Physical synthesis for performance optimization

Proceedings of International Conference on ASIC

Volumn , Issue , 1992, Pages 34-37

  Pokala, R P ^a   Feretich, R A ^a   McGuffin, R W ^a  

^a Vertex Semiconductor ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS;

GATE ARRAYS; HARD-WIRED; IMPROVE PERFORMANCE; PERFORMANCE OPTIMIZATIONS; PHYSICAL SYNTHESIS; ROUTABILITY; SINGLE BIT FLIPS;

LOGIC SYNTHESIS;

EID: 84964819681     PISSN: 21627541     EISSN: 2162755X     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1992.270312     Document Type: Conference Paper

References (6)

1. Alberto Sangiovanni-Vincentelli, "Automatic Layout of Integrated Circuits", Digital Systems for VLSI Circuits, Martinus Nijhoff Publishers, 1987, pp. 113-195.
2. M.A. Breuer, "Design Automation of Digital Systems", Prentice-Hall, 1972.
3. Carl Sechen, "VLSI Placement and Global Routing Using Simulated Annealing", Kluwer Academic Publishers, 1988.
4. B. Preas and P. Karger, "Automatic Placement: A Review of Current Techniques", Proceedings of Design Automation Conference, 1986, pp. 622-629.
5. "IEEE Standard Test Access Port and Boundary Scan Architecture", IEEE Standard 1149.1-1990.
6. Aho, A.V., J.E. Hopcroft, and J.D. Ullman, "The Design and Analysis of Computer Algorithms", Addison-Wesley, Reading Mass., 1974.