Power-aware clock tree planning

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 138-147

  Donno, Monica ^a   Macii, Enrico ^b   Mazzoni, Luca ^c  

^a R and D Division   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c Accent srl   (Italy)

Author keywords

Clock tree synthesis and routing; Low power design; Physical design and optimization

Indexed keywords

CODES (SYMBOLS); COMPUTER HARDWARE; GATES (TRANSISTOR); REDUCED INSTRUCTION SET COMPUTING; TOPOLOGY; TREES (MATHEMATICS);

CLOCK DISTRIBUTION NETWORKS; PROCESSOR POWER; REGISTER TRANSFER LEVEL IMPLEMENTATION; SYSTEM ON CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 2942635242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981097     Document Type: Conference Paper

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