Practical Bounded-Skew Clock Routing

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 199-215

  Kahng, Andrew B ^a,b,c,d   Tsao, C W Albert ^a,d,e,f,g,h  

^a Engineering IV   (United States)

^b HARVARD COLLEGE   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d CADENCE DESIGN SYSTEMS   (United States)

^e NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^f NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^g Ministry of Education   (Taiwan)

^h UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; DIGITAL SIGNAL PROCESSING; HEURISTIC METHODS; TREES (MATHEMATICS);

BUFFERED TREE SYNTHESIS; CLOCK ROUTING;

TIMING CIRCUITS;

EID: 0031163197     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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