Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 395-400

  Shih, Xin Wei ^a   Cheng, Chung Chun ^a   Ho, Yuan Kai ^a   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER INSERTION; CHIP DESIGN; CIRCUIT PERFORMANCE; CLOCK NETWORK SYNTHESIS; CLOCK SKEWS; CLOCK TREE; CLOCK-TREE SYNTHESIS; FIRST-ORDER; PARTICIPATING TEAMS; PROCESS VARIATION; SUPPLY VOLTAGES; THREE-LEVEL; TREE CONSTRUCTION ALGORITHMS; TREE TOPOLOGY;

ADAPTIVE SYSTEMS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; MARINE RISERS; OPTIMIZATION; TELECOMMUNICATION NETWORKS;

TREES (MATHEMATICS);

EID: 77951224766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419850     Document Type: Conference Paper

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