Design space exploration for 3-D Cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 4, 2008, Pages 444-455

  Tsai, Yuh Fang ^a,b   Wang, Feng ^a,b   Xie, Yuan ^a,b   Vijaykrishnan, Narayanan ^b   Irwin, Mary Jane ^a,b  

^a IEEE

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

3 D integrated circuits (ICs); Cache design; Delay energy simulator

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS; SYSTEMS ANALYSIS;

-D INTEGRATED CIRCUITS (IC); DELAY ENERGY SIMULATORS;

SPACE RESEARCH;

EID: 41549104701     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.915429     Document Type: Article

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