A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 869-879

  Takemura, Riichiro ^a   Kawahara, Takayuki ^a   Miura, Katsuya ^a,b   Yamamoto, Hiroyuki ^a   Hayakawa, Jun ^a   Matsuzaki, Nozomu ^a   Ono, Kazuo ^a   Yamanouchi, Michihiko ^a   Ito, Kenchi ^a   Takahashi, Hiromasa ^a   Ikeda, Shoji ^b   Hasegawa, Haruhiro ^a,b   Matsuoka, Hideyuki ^a   Ohno, Hideo ^b  

^a HITACHI LTD   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

2T1R memory cell; Localized bi directional write driver; Low power RAM; Nonvolatile RAM; Spin transfer torque; TMR; Universal memory

Indexed keywords

BI-DIRECTIONAL; LOW POWER; MEMORY CELL; NON-VOLATILE RAMS; SPIN TRANSFER TORQUE;

INTEGRATED CIRCUITS; SPIN DYNAMICS; THERMODYNAMIC STABILITY; THERMOGRAVIMETRIC ANALYSIS;

SEMICONDUCTOR STORAGE;

EID: 77950229376     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2040120     Document Type: Article

References (8)

1. Green IT Initiatives, p. 16. [Online]. Available: http://forum.fujitsu. com/2008/tokyo/seminar/downloads/pdf/k2-seminar.pdf
2. M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, and H. Kano, "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM," in Int. Electron Devices Meeting (IEDM) Tech. Dig., 2005, pp. 459-462.
3. T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, Y. Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, and H. M. Ohno, "2 Mb SPRAM (SPin-Transfer torque RAM) with bit-by-Bit bi-directional current write and parallelizing-direction current read," IEEE J. Solid-State Circuits, vol.43, no.1, pp. 109-120, Jan. 2008.
4. R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, M. Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, and H. Ohno, "32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell," in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 84-85.
5. K. Miura, T. Kawahara, R. Takemura, J. Hayakawa, S. Ikeda, R. Sasaki, H. Takahashi, H. Matsuoka, and H. Ohno, "A novel SPRAM (Spin-transfer torque RAM) with synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write current dispersion," in Symp. VLSI Technology Dig. Tech. Papers, 2007, pp. 234-235.
6. R. Takemura, T. Kawahara, J. Hayakawa, K. Miura, K. Ito, M. Yamanouchi, S. Ikeda, H. Takahashi, H. Matsuoka, and H. Ohno, "TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations," in Proc. Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 Int. Conf. Memory Technology and Design (NVSMW/ICMTD 2008), 2008, pp. 54-56.
7. Z. Li and S. Zhang, "Thermally assisted magnetization reversal in the presence of a spin-transfer torque," Phys. Rev. B, vol.69, p. 134416, 2004.
8. J. DeBrosse, D. Gogl, A. Bette, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Obermaier, W. R. Reohr, H. Viehmann, W. J. Gallagher, and G. Müller, "A high-speed 128-kb MRAM core for future universal memory applications," IEEE J. Solid-State Circuits, vol.39, no.1, pp. 678-683, Jan. 2004.