A 45nm 4Gb 3-dimensional double-slacked multi-level NAND flash memory with shared bitline structure

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 509-511

  Park, Ki Tae ^a   Kim, Doogon ^a   Hwang, Soonwook ^a   Kang, Myounggon ^a   Cho, Hoosung ^a   Jeong, Youngwook ^a   Seo, Yong Il ^a   Jang, Jaehoon ^a   Kim, Han Soo ^a   Jung, Soon Moon ^a   Lee, Yeong Taek ^a   Kim, Changhyun ^a   Lee, Won Seong ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; NAND CIRCUITS; SILICON WAFERS; SINGLE CRYSTALS;

3-DIMENSIONAL; 3D ARCHITECTURES; FLOATING GATES; MULTILEVEL CELL; NAND FLASH MEMORY; PLANAR DEVICES; READ ACCESS TIME; SINGLE-CRYSTAL SI LAYER STACKING;

MEMORY ARCHITECTURE;

EID: 49549094516     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523281     Document Type: Conference Paper

References (9)

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