VLSI architectures for iterative decoders in magnetic recording channels

IEEE Transactions on Magnetics

Volumn 37, Issue 2 I, 2001, Pages 748-755

  Yeo, Engling ^a,b   Pakzad, Payam ^b   Nikolić, Borivoje ^a,b   Anantharam, Venkat ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Iterative decoders; LDPC codes; Magnetic recording; Turbo codes; VLSI architectures

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMMUNICATION CHANNELS (INFORMATION THEORY); DATA STORAGE EQUIPMENT; ITERATIVE METHODS; MAGNETIC RECORDING; MAXIMUM LIKELIHOOD ESTIMATION; TURBO CODES; VLSI CIRCUITS;

ITERATIVE DECODERS;

DECODING;

EID: 0035294983     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/20.917611     Document Type: Article

References (15)

1. Turbo decoding for partial response channels
2. Optimal decoding of linear codes for minimizing symbol error rate
3. Decoding turbo codes with the soft output viterbi algorithm (SOVA)
4. Low density parity check codes
5. Constrained coding techniques for soft iterative decoders
6. VLSI architectures for turbo codes
7. The influence of quantization and fixed point arithmetic upon the BER performance of turbo codes
8. Weight distributions for turbo codes using random and nonrandom permutations
9. Interleaver design methods for turbo codes
10. A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain
11. An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes
12. A low complexity soft-output viterbi decoder architecture
13. Evaluation of gallager codes for short block length and high rate applications
14. Low density parity check codes based on finite geometries: A rediscovery
15. Early detection and trellis splicing: Reduced-complexity iterative decoding