High-speed map architecture with optimized memory size and power consumption

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2000, Pages 265-274

  Worm, Alexander ^a   Lamm, Holger ^a   Wehn, Norbert ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONVOLUTIONAL CODES; DECODING; MAXIMUM LIKELIHOOD ESTIMATION; OPTIMIZATION; SIGNAL PROCESSING; TURBO CODES;

LOG LIKELIHOOD RATIO; MAXIMUM A POSTERIORI ALGORITHM; MEMORY SIZE; POWER CONSUMPTION; VITERBI ALGORITHM;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0034515302     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)