VLSI architectures for turbo codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 3, 1999, Pages 369-379

  Masera, Guido ^a,b   Piccinini, Gianluca ^b   Roch, Massimo Ruo ^b   Zamboni, Maurizio ^a,b  

^a IEEE   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

TURBO CODES;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; DECODING; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS;

VLSI CIRCUITS;

EID: 0032646197     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784098     Document Type: Article

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