FPGA implementation of a 3GPP turbo codec

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2001, Pages 61-65

  Steensma, Johannes ^a   Dick, Chris ^b  

^a Adelante Technologies   (Australia)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; C (PROGRAMMING LANGUAGE); CONVOLUTIONAL CODES; DECODING; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); ERROR CORRECTION; LOGIC GATES; SIGNAL TO NOISE RATIO; TURBO CODES; WIRELESS TELECOMMUNICATION SYSTEMS;

FORWARD ERROR CONTROL; TURBO CODEC; TURBO CONVOLUTIONAL CODES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035573962     PISSN: 10586393     EISSN: None     Source Type: Journal    
DOI: 10.1109/ACSSC.2001.986881     Document Type: Article

References (9)

1. A primer on turbo code concepts
2. Near shannon limit error-correcting coding and decoding: Turbo codes
3. Optimal decoding of linear codes for minimizing symbol error rate