Architectural strategies for low-power VLSI turbo decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 3, 2002, Pages 279-285

  Masera, Guido ^a   Mazza, Marco ^a   Piccinini, Gianluca ^a   Viglione, Fabrizio ^a   Zamboni, Maurizio ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

High performance; Low voltage; Low power design; Memory; Partitioning; Turbo decoding; Very large scale integration (VLSI)

Indexed keywords

CONSTRAINT THEORY; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; RANDOM ACCESS STORAGE; SIGNAL TO NOISE RATIO; TURBO CODES; WIRELESS TELECOMMUNICATION SYSTEMS;

CODING GAINS; POWER DISSIPATION; TURBO DECODERS;

VLSI CIRCUITS;

EID: 0036625313     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043330     Document Type: Article

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