Area-efficient high-speed decoding schemes for turbo decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 902-912

  Wang, Zhongfeng ^a   Chi, Zhipei ^b   Parhi, Keshab K ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Area efficient; High speed; Maximum a posteriori (MAP) algorithm; Parallel decoding; Turbo code; Very large scale integration (VLSI)

Indexed keywords

COMPUTER SIMULATION; ITERATIVE METHODS; PARALLEL PROCESSING SYSTEMS; THROUGHPUT; VLSI CIRCUITS;

TURBO DECODERS;

DECODING;

EID: 0036927792     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808451     Document Type: Article

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