Implementation of a parallel turbo decoder with dividable interleaver

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Kwak, Jaeyoung ^a   Park, Sook Min ^a   Yoon, Sang Sic ^a   Lee, Kwyro ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; VLSI CIRCUITS;

TURBO DECODER;

DECODING;

EID: 17144472503     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. A. Giulietti, B. Bougard, V. Derudder, et. al, "A 80 Mb/s low-power scalable turbo codec core," IEEE Custom Integrated Circuits Conference, pp. 389-392, 2002.