A simplified and efficient implementation of FPGA-based turbo decoder

IEEE International Performance, Computing and Communications Conference, Proceedings

Volumn , Issue , 2003, Pages 207-213

  Sharma, Sanjay ^a   Attri, Sanjay ^b   Chauhan, R C ^a  

^a SANT LONGOWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY   (India)

^b ITTI   (India)

Author keywords

FPGA; Max log MAP; Metric normalization; Quantization; Sub block processing; Turbo decoder

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIT ERROR RATE; CODE DIVISION MULTIPLE ACCESS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; SIGNAL TO NOISE RATIO; CHANNEL CODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FIXED POINT ARITHMETIC; HARDWARE; RECONFIGURABLE HARDWARE;

METRIC NORMALIZATION; SUB-BLOCK PROCESSING; TURBO DECODER;

DECODING;

MAX-LOG-MAP; METRIC NORMALIZATION; QUANTIZATION; SUB-BLOCKS; TURBO DECODERS;

EID: 84983103128     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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