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Volumn , Issue , 2003, Pages

A 24 Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DATA STRUCTURES; DECODING; MOBILE TELECOMMUNICATION SYSTEMS; TRELLIS CODES;

EID: 0037630985     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (103)

References (6)
  • 1
    • 84886716036 scopus 로고    scopus 로고
    • Physical layer aspects of UTRA high speed downlink packet access
    • 3GPP TR25.848 V4.0.0(2001-03)
    • 3GPP TR25.848 V4.0.0(2001-03), "Physical Layer Aspects of UTRA High Speed Downlink Packet Access".
  • 2
    • 0003439647 scopus 로고    scopus 로고
    • Stopping rules for turbo decoders
    • JPL TMO Progress Report; Aug.
    • A. Matache et-al, "Stopping Rules for Turbo Decoders", JPL TMO Progress Report, 42-142, Aug. 15, 2000.
    • (2000) , pp. 42-142
    • Matache, A.1
  • 3
    • 0034878272 scopus 로고    scopus 로고
    • Energy efficient turbo decoding for 3G mobile
    • D. Garrett, et-al, "Energy Efficient Turbo Decoding for 3G Mobile", Int. Symp. Low Power Electr. and Design, pp. 328-333, 2001.
    • (2001) Int. Symp. Low Power Electr. and Design , pp. 328-333
    • Garrett, D.1
  • 4
    • 0036116429 scopus 로고    scopus 로고
    • A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18μm CMOS
    • Feb.
    • M. Bickerstaff, et-al "A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18μm CMOS", ISSCC Dig. Tech. Papers, pp. 124-125, Feb. 2002.
    • (2002) ISSCC Dig. Tech. Papers , pp. 124-125
    • Bickerstaff, M.1
  • 5
    • 0032646197 scopus 로고    scopus 로고
    • VLSI architectures for turbo codes
    • G. Masera et-al, "VLSI Architectures for Turbo Codes", IEEE Trans. VLSI Sys., vol. 7, No. 3, 1999, pp. 369-379.
    • (1999) IEEE Trans. VLSI Sys. , vol.7 , Issue.3 , pp. 369-379
    • Masera, G.1
  • 6
    • 0028372012 scopus 로고
    • Reduced complexity symbol detectors with parallel structures for ISI channels
    • J. Erfanian, et-al, "Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels", IEEE Trans. Comms, vol. 42, pp. 1661-1671, 1994.
    • (1994) IEEE Trans. Comms , vol.42 , pp. 1661-1671
    • Erfanian, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.