A 50 mbit/s iterative turbo-decoder

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 176-180

  Viglione, F ^a   Masera, G ^a   Piccinini, G ^a   Ruo Roch, M ^a   Zamboni, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SOLUTIONS; DECODING DELAY; HIGH PERFORMANCE COMMUNICATION; HSPICE SIMULATIONS; LOW SIGNAL-TO-NOISE RATIO; TRUE-SINGLE-PHASE-CLOCKING; TURBO DECODERS; VHDL SIMULATION;

CLOCKS; EXHIBITIONS; THROUGHPUT;

DESIGN;

EID: 0141859010     PISSN: 15301591     EISSN: None     Source Type: Journal    
DOI: 10.1109/DATE.2000.840035     Document Type: Article

References (11)

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