VLSI Architectures for SISO-APP Decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 627-650

  Mansour, Mohammad M ^a   Shanbhag, Nares R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Iterative decoders; Soft input soft output a posteriori probability (SISO APP) algorithm; Turbo codes; Very large scale integration (VLSI) architectures

Indexed keywords

ALGORITHMS; DECODING; PROBABILITY; TURBO CODES;

DECODERS;

VLSI CIRCUITS;

EID: 0141620329     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.816136     Document Type: Article

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