Mapping interleaving laws to parallel turbo decoder architectures

IEEE Communications Letters

Volumn 8, Issue 3, 2004, Pages 162-164

  Tarable, Alberto ^a   Benedetto, S ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Interleaver; Memory mapping; Parallel implementation; Turbo codes

Indexed keywords

ALGORITHMS; CONFORMAL MAPPING; CONSTRAINT THEORY; CONVOLUTIONAL CODES; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; ITERATIVE METHODS; MATRIX ALGEBRA; RANDOM PROCESSES;

INTERLEAVER; MEMORY MAPPING; PARALLEL IMPLEMENTATION;

TURBO CODES;

EID: 1942424194     PISSN: 10897798     EISSN: None     Source Type: Journal    
DOI: 10.1109/LCOMM.2004.823364     Document Type: Article

References (5)

1. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correction coding and decoding: Turbo-codes," in Proc. 1993 Int. Conf. on Communications (ICC'93), 1993, pp. 1064-1070.
2. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks," Eur. Trans. Telecommun., vol. 9, Mar.-Apr. 1998.
3. ____, "Serial concatenation of interleaved codes: Performance analysis, design and iterative decoding," IEEE Trans. Inform. Theory, vol. 44, pp. 909-926, June 1998.
4. B. Bougard, A. Giulietti, L. Van der Perre, and F. Catthoor, "A class of power efficient VLSI architectures for high-speed turbo-decoding," in Proc. Global Conf. on Communications (GLOBECOM 2002), Taipei, 2002.
5. A. Tarable, G. Montorsi, and S. Benedetto. (2003) Mapping interleaving laws on parallel turbo decoder architecture. Internal Report, Dip. Elettronica-Politecnico, Turin, Italy. [Online]. Available: www.comm-group.polito.it/Personal/Tarable/articoli/mapping/pdf.