An overview of physical analysis of nanosize conductive path in ultrathin SiON and high-κ gate dielectrics in nanoelectronic devices

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2010, Pages

  Pey, K L ^a   Wu, X ^a   Liu, W H ^a,b   Li, X ^a   Raghavan, N ^a   Shubhakar, K ^a   Bosman, M ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Failure analysis; Filamentation; High dielectric; Interfacial layer; Metal gate; Percolation; Post breakdown; Random telegraph noise (RTN); Switching; Time dependent dielectric breakdown (TDDB)

Indexed keywords

FILAMENTATION; INTERFACIAL LAYER; METAL GATE; PERCOLATION; POST-BREAKDOWN; RANDOM TELEGRAPH NOISE; TIME DEPENDENT DIELECTRIC BREAKDOWN;

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRON EMISSION; ENERGY DISSIPATION; FAILURE ANALYSIS; GATE DIELECTRICS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; LEAKAGE (FLUID); LEAKAGE CURRENTS; LOGIC GATES; METAL ANALYSIS; NANOELECTRONICS; PHOTODEGRADATION; QUALITY ASSURANCE; SCANNING TUNNELING MICROSCOPY; SOLVENTS; TELEGRAPH; TRANSMISSION ELECTRON MICROSCOPY; X RAY SPECTROSCOPY;

ELECTRON ENERGY LOSS SPECTROSCOPY;

EID: 77956440156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2010.5531983     Document Type: Conference Paper

References (39)

1. E. Y. Wu, J. H. Stathis, and L. K. Han, Ultra-thin oxide reliability for ULSI applications. Semiconductor Science and Technologyy, 2000. 15(5): p. 425-435.
2. J. Wang, H. P. Li, and R. Stevens, Hafnia and hafnia-toughened ceramics. Journal of Materials Science, 1992. 27(20): p. 5397-5430.
3. M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, Application of HfSiON as a gate dielectric material. Applied Physics Letters, 2002. 80(17): p. 3183.
4. X. P. Wang, M. F. Li, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, J. Ning, M. B. Yu, and D. L. Kwong, Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs. IEEE Electron Device Letters, 2006. 27(1): p. 31-33.
5. 2 high-k gate dielectrics directly grown on Si (111). Applied Physics Letters, 2002. 81(23): p. 4386-4388.
6. 2 based high-k gate dielectrics as a candidate for low power applications, in Symposium on VLSI Technology. 2004. p. 190-191.
7. J. Robertson, High dielectric constant gate oxides for metal oxide Si transistors. Reports on Progress in Physics, 2006. 69(2): p. 327-396.
8. X. Li, K. L. Pey, M. Bosman, W. H. Liu, and T. Kauerauf, Direct visualization and in-depth physical study of metal filament formation in percolated high-k dielectrics. Applied Physics Letters, 2010. 96(2): p. 022903-3.
9. K. L. Pey, N. Raghavan, X. Li, W. H. Liu, K. Shubhakar, X. Wu, and M. Bosman, New Insight into the TDDB and Post Breakdown Reliability of Novel High-κ Gate Dielectric Stacks, in IEEE International Reliability Physics Symposium (IRPS). 2010: accepted.
10. 2-based gate stack breakdown. Applied Physics Letters, 2010. 96(17): p. 172901.
11. N. Raghavan, X. Wu, X. Li, W. H. Liu, V. L. Lo, and K. L. Pey, Post breakdown reliability enhancement of ULSI circuits with novel gate dielectric stacks, in IEEE International Symposium on Integrated Circuits (ISIC). 2009. p. 505-513.
12. C. H. Tung, K. L. Pey, L. J. Tang, M. K. Radhakrishnan, W. H. Lin, F. Palumbo, and S. Lombardo, Percolation path and dielectric-breakdown-induced- epitaxy evolution during ultrathin gate dielectric breakdown transient. Applied Physics Letters, 2003. 83(11): p. 2223-2225.
13. C. H. Tung, K. L. Pey, L. J. Tang, Y. Cao, M. K. Radhakrishnan, and W. H. Lin, Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance. IEEE Transactions on Electron Devices, 2005. 52(4): p. 473-483.
14. K. Shubhakar, K. L. Pey, S. S. Kushwaha, S. J. O'Shea, M. Bosman, M. Kouda, K. Kakushima, and H. Iwai, Localized degradation and breakdown study of cerium-oxide high-κ gate dielectric material using scanning tunneling microscopy, in International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). 2010: accepted.
15. W. J. Kaiser and L. D. Bell, Direct investigation of subsurface interface electronic structure by ballistic-electron-emission microscopy. Physical Review Letters, 1988. 60(14): p. 1406.
16. L. D. Bell and W. J. Kaiser, Observation of Interface Band Structure by Ballistic-Electron-Emission Microscopy. Physical Review Letters, 1988. 61(20): p. 2368.
17. V. Grosse, R. Bechstein, F. Schmidl, and P. Seidel, Conductivity and dielectric properties of thin amorphous cerium dioxide films. Journal of Physics D: Applied Physics, 2007. 40(4): p. 1146-1149.
18. 2 gate dielectrics with rapid thermal annealing, in Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004. 2004. p. 161-164.
19. M. S. Rahman, E. K. Evangelou, I. I. Androulidakis, and A. Dimoulas, Current transport mechanism in high-κ cerium oxide gate dielectrics grown on germanium substrates. Electrochemical and Solid-State Letters, 2009. 12(5).
20. G. D. Wilk, R. M. Wallace, and J. M. Anthony, High-κ gate dielectrics: Current status and materials properties considerations. Journal of Applied Physics, 2001. 89(10): p. 5243-5275.
21. 2/metal gate stacks under positive Constant Voltage Stress, in IEEE International Electron Device Meeting (IEDM). 2005. p. 408-411.
22. N. Raghavan, K. L. Pey, and X. Li, Detection of high-κ and interfacial layer breakdown using the tunneling mechanism in a dual layer dielectric stack. Applied Physics Letters, 2009. 95(22).
23. 2 high-k/polycrystalline silicon gate stacks. Applied Physics Letters, 2005. 87(24): p. 242907-3.
24. J. S. Suehle, B. Zhu, Y. Chen, and J. B. Bernstein, Acceleration factors and mechanistic study of progressive breakdown in small area ultra-thin gate oxides, in IEEE International Reliability Physics Symposium (IRPS). 2004. p. 779-782.
25. V. L. Lo, K. L. Pey, C. H. Tung, and D. S. Ang, A critical gate voltage triggering irreversible gate dielectric degradation, in IEEE International Reliability Physics Symposium (IRPS). 2007. p. 576-577.
26. V. L. Lo, K. L. Pey, C. H. Tung, and X. Li, Multiple digital breakdowns and its consequence on ultrathin gate dielectrics reliability prediction, in IEEE International Electron Device Meeting (IEDM). 2007. p. 497-500.
27. X. Li, C. H. Tung, K. L. Pey, and V. L. Lo, The physical origin of random telegraph noise after dielectric breakdown. Applied Physics Letters, 2009. 94(13).
28. B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van De Mieroop, V. Simons, and G. Groeseneken, Consistent model for short-channel nMOSFET after hard gate oxide breakdown. IEEE Transactions on Electron Devices, 2002. 49(3): p. 507-513.
29. X. Li, C. H. Tung, K. L. Pey, and V. L. Lo, The chemistry of gate dielectric breakdown, in IEEE International Electron Device Meeting (IEDM). 2008. p. 779-782.
30. X. Li, C. H. Tung, and K. L. Pey, The nature of dielectric breakdown. Applied Physics Letters, 2008. 93(7).
31. 2. Physical Review Letters, 2007. 99(15).
32. F. Monsieur, E. Vincent, G. Ribes, V. Huard, S. Bruyère, D. Roy, G. Pananakakis, and G. Ghibaudo, Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides, in IEEE International Reliability Physics Symposium (IRPS). 2003. p. 424-431.
33. F. Monsieur, E. Vincent, D. Roy, S. Bruyere, J. C. Vildeuil, G. Pananakakis, and G. Ghibaudo, A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment, in IEEE International Reliability Physics Symposium (IRPS). 2002. p. 45-54.
34. B. P. Linder, S. Lombardo, J. H. Stathis, A. Vayshenker, and D. J. Frank, Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics. IEEE Electron Device Letters, 2002. 23(11): p. 661-663.
35. T. Kauerauf, R. Degraeve, M. B. Zahid, M. Cho, B. Kaczer, Ph Roussel, G. Groeseneken, H. Maes, and S. De Gendt Abrupt breakdown in dielectric/metal gate stacks: A potential reliability limitation? IEEE Electron Device Letters, 2005. 26(10): p. 773-775.
36. 2/TaN/TiN gate stack MOSFET, in IEEE International Electron Device Meeting (IEDM). 2006. p. 759-763.
37. W. H. Liu, K. L. Pey, X. Li, and M. Bosman, Observation of Switching Behaviors in Post-Breakdown Conduction in NiSi-gated Stacks, in IEEE International Electron Device Meeting (IEDM). 2009. p. 135-139.
38. N. Raghavan, K. L. Pey, W. H. Liu, X. Wu, and X. Li, Unipolar recovery of dielectric breakdown in fully silicided high-kappa gate stack devices and its reliability implications. Applied Physics Letters, 2010. 96(14): p. 142901.
39. X. Wu, K. L. Pey, G. Zhang, P. Bai, X. Li, W. H. Liu, and N. Raghavan, Electrode material dependent breakdown and recovery in advanced high-κ gate stacks. Applied Physics Letters, 2010 (accepted).