Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

IEEE Transactions on Electron Devices

Volumn 52, Issue 4, 2005, Pages 473-483

  Tung, Chih Hang ^a   Pey, Kin Leong ^b   Tang, L J ^a,b   Cao, Y ^c   Radhakrishnan, M K ^d   Lin, W H ^e  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^d NanoRel   (Singapore)

^e CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

(SBD); Dielectric breakdown (DB); Dielectric breakdown induced epitaxy (DBIE); Gate oxide reliability; Hard and soft breakdown (HBD); Modeling; Narrow MOSFET; Transmission electron microscopy (TEM)

Indexed keywords

COMPUTER SIMULATION; DEGRADATION; DIELECTRIC PROPERTIES; ELECTRIC BREAKDOWN; ELECTRIC VARIABLES MEASUREMENT; ELECTRODES; GATES (TRANSISTOR); RELIABILITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; TRANSMISSION ELECTRON MICROSCOPY; ULTRATHIN FILMS;

DEVICE PERFORMANCE; DIELECTRIC BREAKDOWN (DB); DIELECTRIC BREAKDOWN INDUCED EPITAXY (DBIE); GATE ELECTRODE; GATE OXIDE RELIABILITY; POST BREAKDOWN (BD) DEGRADATION; SILICON SUBSTRATE; ULTRATHIN GATE OXIDE;

MOSFET DEVICES;

EID: 17444392476     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.844763     Document Type: Article

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