Post breakdown reliability enhancement of ULSI circuits with novel gate dielectric stacks

ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Volumn , Issue , 2009, Pages 505-513

  Raghavan, N ^a   Wu, X ^a   Li, X ^a   Liu, W H ^a   Lo, V L ^a,b   Pey, K L ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

Circuit reliability; Device reliability; Digital breakdown (Di BD); Monte Carlo simulation; Post breakdown; Time dependent dielectric breakdown (TDDB); Weibull distribution

Indexed keywords

ACCELERATED LIFE TESTS; BREAKDOWN TIME; CIRCUIT LEVELS; CIRCUIT PERFORMANCE; CIRCUIT RELIABILITY; CURRENT DRIVES; DEVICE RELIABILITY; ELECTRICAL CHARACTERIZATION; FAILURE DATA; FAN-OUT; GATE CURRENT; GATE DIELECTRIC STACKS; KEY PERFORMANCE INDICATORS; LIFETIME ENHANCEMENT; MONTE CARLO SIMULATION; MONTE CARLO SIMULATION TECHNIQUE; PERFORMANCE PARAMETERS; POWER DISSIPATION; RANDOM TELEGRAPH NOISE; RELIABILITY ENHANCEMENT; STATISTICAL TOOLS; TIME DEPENDENT DIELECTRIC BREAKDOWN; TWO STAGE; ULTRATHIN GATE DIELECTRICS;

BENCHMARKING; CARRIER MOBILITY; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC NETWORK ANALYSIS; GATE DIELECTRICS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MONTE CARLO METHODS; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; STATISTICAL MECHANICS; TELEGRAPH; TESTING; ULSI CIRCUITS; WEIBULL DISTRIBUTION;

DIELECTRIC MATERIALS;

EID: 77950451659     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. M. Lundstrom, "Moore's Law Forever?", Science, Vol.299, No.5604, pp.210-211, (2003).
2. International Technology Roadmap for Semiconductors (ITRS). (2008).
3. G. Ribes, M. Rafik and D. Roy, "Reliability issues for nano-scale CMOS dielectrics", Microelectronic Engineering, Vol.84, pp.1910-1916, (2007).
4. G.D. Wilk, R.M. Wallace and J.M. Anthony, "High-κ gate dielectrics - Current status and materials properties considerations", Applied Physics Review, Journal of Applied Physics, Vol.89, No.10, pp.5243-5275, (2001).
5. J. Sune, E.Y. Wu and W.L. Lai, "Statistics of competing post-breakdown failure modes in ultrathin MOS devices", IEEE Transactions on Electron Devices, Vol.53, No.2, pp.224-234, (2006).
6. G. Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra and R. Choi, "Progressive breakdown characteristics of high-κ / metal gate stacks", IEEE International Reliability Physics Symposium (IRPS), pp.49-54, (2007).
7. 2 films", IEEE Transactions on Electron Devices, Vol.ED-32, No.2, pp.423-428, (1985).
8. X. Li, C.H. Tung, K.L. Pey and V.L. Lo, "The chemistry of gate dielectric breakdown", IEEE International Electron Device Meeting (IEDM), pp.779-782, (2008).
9. J.S. Suehle, B. Zhu, Y. Chen and J.B. Bernstein, "Acceleration factors and mechanistic study of progressive breakdown in small area ultra-thin gate oxides", IEEE International Reliability Physics Symposium (IRPS), pp.95-101, (2004).
10. T.A.L. Selvarajoo, R. Ranjan, K.L. Pey, L.J. Tang, C.H. Tung and W. Lin, "Dielectric-breakdown induced epitaxy - A universal breakdown defect in ultrathin gate dielectrics", IEEE Transactions on Device and Materials Reliability, Vol.5, No.2, pp.190-197, (2005).
11. E.Y. Wu, J. Sune, B.P. Linder, J.H. Stathis and W.L. Lai, "Critical assessment of soft breakdown stability time and the implementation of new post breakdown methodology for ultra-thin gate oxides", IEEE International Electron Device Meeting (IEDM), pp.919-922, (2003).
12. V.L. Lo, K.L. Pey, C.H. Tung and D.S. Ang, "A critical gate voltage triggering irreversible gate dielectric degradation", IEEE International Reliability Physics Symposium (IRPS), pp.576-577, (2007).
13. X. Li, C.H. Tung and K.L. Pey, "The nature of dielectric breakdown", Applied Physics Letters, 93, 072903, (2008).
14. X. Li, C.H. Tung and K.L. Pey, "The physical origin of random telegraph noise after dielectric breakdown", Applied Physics Letters, 94, 132904, (2009).
15. C.H. Tung, K.L. Pey, L.J. Tang, M.K. Radhakrishnan, W.H. Lin, F. Palumbo and S. Lombardo, "Percolation path and dielectric-breakdowninduced- epitaxy evolution during ultrathin gate dielectric breakdown transient", Applied Physics Letters, Vol.83, No.11, pp.2223-2225, (2003).
16. R. Ranjan, K.L. Pey, C.H. Tung, D.S. Ang, L.J. Tang, T. Kauerauf, R. Degraeve, G. Groeseneken, S. De Gendt and L.K. Bera, "Failure defects observed in post-breakdown high-κ/metal gate stack MOSFET", IEEE International Reliability Physics Symposium (IRPS), pp.590-594, (2006).
17. W. Luo, "Reliability characterization and prediction of high-κ dielectric thin film", PhD Thesis, Texas A&M University, (2004).
18. X. Li, C.H. Tung and K.L. Pey, "The radial distribution of defects in a percolation path", Applied Physics Letters, 93, 262902, (2008).
19. B. Kaczer, R. Degraeve, M. Rasras, K.V. de Mieroop, P.J. Roussel and G. Groeseneken, "Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability", IEEE Transactions on Electron Devices, Vol.49, No.3, pp.500-506, (2002).
20. 2 gate dielectric", IEEE International Reliability Physics Symposium (IRPS), pp.347-352, (2004).
21. T. Pompl and M. Kerber, "Failure distributions of successive dielectric breakdown events", IEEE Transactions on Device and Materials Reliability, Vol.4, No.2, pp.263-267, (2004).
22. 2 high-κ gate stacks", IEEE International Electron Device Meeting (IEDM), pp.725-728, (2004).
23. S. Sahhaf, R. Degraeve, P.J. Roussel, B. Kaczer, T. Kauerauf, "A new TDDB reliability prediction methodology accounting for multiple SBD and wear out", IEEE Transactions on Electron Devices, Vol.56, No.7, pp.1424-1432, (2009).
24. M.A. Alam, R.K. Smith, B.E. Weir and P.J. Silverman, "Statistically independent soft breakdowns redefine oxide reliability specifications", IEEE International Electron Device Meeting (IEDM), pp.919-922, (2003).
25. J. Martin-Martinez, B. Kaczer et. al., Proc. Spanish Conf. Electron. Dev, 156, (2009).
26. R. Rodriguez, J.H. Stathis, B.P. Linder, S. Kowalczyk, C.T. Chuang, R.V. Joshi, G. Northrop, K. Bernstein, A.J. Bhavnagarwala and S. Lombardo, "The impact of gate-oxide breakdown on SRAM stability", IEEE Electron Device Letters, Vol.23, No.9, pp.559-561, (2002).
27. B. Kaczer, R. Degraeve, M. Rasras, A. De Keersgieter, K. Van de Mieroop and G. Groeseneken, "Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study", Microelectronics Reliability, Vol.42, Issues 4-5, pp.555-564, (2002).