Optimized self-tuning for circuit aging

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 586-591

  Mintarno, Evelyn ^a   Skaf, Joëlle ^a   Zheng, Rui ^b   Velamala, Jyothi ^b   Cao, Yu ^b   Boyd, Stephen ^a   Dutton, Robert W ^a   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTATIONAL EFFICIENCY; TIMING CIRCUITS;

BENCHMARK CIRCUIT; COMPUTATIONAL POWER; DESIGN CONSTRAINTS; NUMBER OF CLOCK CYCLES; OPTIMIZED CONTROL; PERFORMANCE CONSTRAINTS; RECOVERY EFFECTS; SELF TUNING PARAMETERS;

TUNING;

EID: 77953113043     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457140     Document Type: Conference Paper

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