Circuit techniques for subthreshold leakage avoidance, control, and tolerance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 421-424

  Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CIRCUIT THEORY; COMPUTER ARCHITECTURE; LEAKAGE CURRENTS; ROBUSTNESS (CONTROL SYSTEMS); TRANSISTORS; TIMING CIRCUITS;

BODY BIAS; BRUTE-FORCE SWITCHES; SLEEP TRANSISTORS; STACK EFFECTS; STACK FORCING; SUBTHRESHOLD LEAKAGE POWER; SUPPLY VOLTAGE;

THRESHOLD VOLTAGE;

CIRCUIT DESIGNERS; CIRCUIT TECHNIQUES; ENTIRE SYSTEM; SCALE-DOWN; SUB-THRESHOLD LEAKAGE; SUBTHRESHOLD LEAKAGE POWER; SUPPLY VOLTAGES;

EID: 21644486110     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. L Wei, et al, VLSI 2000,13th Int. Conference on VLSI Design
2. A. Keshavarzi et. al., ISLPED 2001
3. A. Keshavarzi et. al., ISLPED 1999
4. S. Narendra et al, ISSCC 2002
5. J. Tschanz et al, ISSCC 2002
6. S. Narendra et. al., ISLPED 2001
7. Y. Ye et. al, Symp. VLSI Circuits 1998
8. J. Tschanz et al, ISSCC 2003
9. A. Alvandpour et. al., Symp. VLSI Circuits 2001
10. R. Krishnamurthy et. al., Symp. VLSI Circuits 2001