Optimized circuit failure prediction for aging: Practicality and promise

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Agarwal, Mridul ^a   Balakrishnan, Varsha ^b   Bhuyan, Anshuman ^c   Kim, Kyunglok ^c   Paul, Bipul C ^c   Wang, Wenping ^b   Yang, Bo ^b   Cao, Yu ^b   Mitra, Subhasish ^c  

^a AMD ^*

^b ARIZONA STATE UNIVERSITY   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGING MECHANISM; CHIP-LEVEL; CIRCUIT FAILURES; CMOS RELIABILITY; FLIP-FLOP DESIGNS; ON-CHIP CIRCUITS; SYSTEM OPERATION; TEST CHIPS; TIMING ANALYSIS;

FLIP FLOP CIRCUITS; QUALITY ASSURANCE; SENSORS; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 67249159156     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700619     Document Type: Conference Paper

References (15)

1. [Agarwal 07] M. Agarwal, et al., "Circuit Failure Prediction and Its Application to Transistor Aging," IEEE VLSI Test Symp., 2007.
2. [Bhardwaj 06] S. Bhardwaj, et al., "Predictive Modeling of the NBTI Effect for Reliable Design," IEEE Custom Integrated Circuits Conf., 2006.
3. [Borkar 06] S. Borkar, "Electronics beyond nano-scale CMOS," ACM/IEEE Design Automation Conf., 2006.
4. [Chen 03] G. Chen, et al., "Dynamic NBTI of PMOS transistors and its impact on device lifetime," International Reliability Physics Symp., 2003.
5. [Grasser 07] T. Grasser, et al., "Simultaneous extraction of recoverable and permanent components contributing to biastemperature instability," International Electron Device Meeting, 2007.
6. [Huard 06] V. Huard, et al., "NBTI degradation: From physical mechanisms to modeling," Microelectronics Reliability, Jan 2006, vol.46, no. 1, pages1-23.
7. [Huard 07] V. Huard, et al., "New characterization and modeling approach for NBTI degradation from transistor to product level," International Electron Device Meeting, 2007.
8. [Inoue 08] H. Inoue, Y. Li and S. Mitra, "VAST: Virtualization Assisted Concurrent Autonomous Self-Test," Intl. Test Conf., 2008.
9. [Kuhn 08] K. Kuhn et al., "Managing Process Variation in Intel's 45nm CMOS Technology," Intel Technology Journal, June 2008.
10. [Li 08] Y. Li, S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns," Design Automation and Test in Europe, 2008.
11. [Mitra 08a] S. Mitra, "Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges," Design Automation and Test in Europe, 2008.
12. [Mitra 08b] S. Mitra, "Circuit Failure Prediction for Robust System Design in Scaled CMOS," International Reliability Physics Symp., 2008.
13. [Shroder 03] D. K. Schroder, et al, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," Journal of Applied Physics, 2003.
14. [Wang 07a] W. Wang, et al., "The impact of NBTI on the performance of combinational and sequential circuits," Design Automation Conf., 2007.
15. [Wang 07b] W. Wang, et al., "Compact Modeling and Simulation of Circuit Reliability for 65nm CMOS Technology," IEEE Trans. Device and Materials Reliability, 2007.