CASP: Concurrent autonomous chip self-test using stored test patterns

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 885-890

  Li, Yanjing ^a   Makar, Samy ^b   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

^b CSwitch Corporation

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; END USERS; ENTIRE SYSTEM; FAILURE PREDICTION; MULTI CORES; NON-VOLATILE MEMORIES; NORMAL OPERATION; RELIABILITY CHALLENGES; ROBUST SY STEMS; SELF REPAIRING; SELF TESTING; SELF-DIAGNOSIS; SYSTEM OPERATIONS; SYSTEM-LEVEL SUPPORT; TEST PATTERNS;

DATA STORAGE EQUIPMENT; ERROR DETECTION; INDUSTRIAL ENGINEERING; MAINTENANCE;

TESTING;

EID: 49749112001     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484786     Document Type: Conference Paper

References (50)

1. Agarwal M., B. Paul, M. Zhang, and S. Mitra, "Circuit Failure Prediction and Its Application to Transistor Aging," IEEE VLSI Test Symp., pp. 277-286, 2007.
2. Al-Asaad, H., B.T. Murray, and J.P. Hayes, "Online BIST for Embedded Systems," IEEE Design & Test of Computers, pp.17-24, 1998.
3. "AMD Multicore Technology Evolution," http://multicore.amd.com/ us-en/AMD-Multi-Core/Technology-Evolution.aspx.
4. "Azul Systems First to Deliver 48-Way Multicore Chip, Redefining Standard in Enterprise Computing," http://www.azulsystems.com/press/ 032706_vega2.htm
5. Bardell, P.H., W.H. McAnney, and J. Savir, Buit-In Test for VLSI: Pseudorandom Techniques, Wiley, 1987.
6. Bardell P.H., and M.J. Papointe, "Production Experience with Built-In Self-Test," Proc. Intl. Test Conf., pp. 28-36, 1991.
7. Bernick, D., et al., "Non-Stop Advanced Architecture," Intl. Conf. Dependable Systems and Networks, pp. 12-21, 2005.
8. Bonhomme, Y., et al., "A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores," Proc. Asian Test Symp., pp. 253-258, 2001.
9. Borkar, S., "Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation," IEEE Micro, Vol. 25, Issue 6, pp. 10-16, 2005.
10. Borkar, S., "Thousand Core Chips - A Technology Perspective," Proc. Design Automation Conf., pp. 746-749, 2007.
11. Breuer, M., and A. Ismaeel, "Roving Emulation as a Fault Detection Mechanism," IEEE Trans. Comput., pp. 933-939, 1986.
12. "Delay Test Methods in Encounter Test," http://sourcelink. cadence.com/docs/files/Application_Notes/2004/EncounterTest_delay_test.pdf.
13. Chandra, A., and K., Chakrabarty, "Low-Power Scan Testing and Test Data Compresiion for System-on-a-Chip," IEEE Trans. CAD, pp. 597-604, 2002.
14. Chen, L., et al., "A Scalable Software-based Self-test Methodology for Programmable Processors," Proc. Design Automation Conf., pp. 548-553, 2003.
15. http://newsroom.cisco.com/dlls/partners/news/2004/pr_prod_06-09.html
16. Constantinides, K., et al., "BulletProof: A Defect-Tolerant CMP Switch Architecture," Proc. Intl. Symp. High-Performance Computer Architecture, 2006.
17. Corno, M., et al., "On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications," European Dependable Computing Conf., pp. 190-202, 1996.
18. http://www.dell.com/content/topics/global.aspx/corp/pressoffice/en/2007/ 2007_04_24_rr_000?c=us&l=en&s=corp.
19. Gray, J., and B. Fitzgerald, "FLASH Disk Opportunity for Sever Applications," http://research.microsoft.com/∼Gray/papers/ FlashDiskPublic.doc.
20. Gupta, S.K., and D. Pradhan, "Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa," IEEE Trans. Computers, pp. 63-73, 1996.
21. "POWER processor-based blade servers," http://www-03.ibm.com/ systems/bladecenter/power-based.html
22. Inoue, H., et al., "Dynamic Security Domain Scaling on Symmetric Multiprocessors for Future High-End Embedded Systems," Proceedings of Intl. Conf. on CODES & ISSS, pp. 39-44, 2007.
23. "Intel Multicore," http://www.intel.com/multi-core.
24. Iyengar, V., et al., "At-Speed Structural Test for High-Performance ASICs," Proc. Intl. Test Conf., pp. 1-10, 2006.
25. Karri, R., and N. Mukherjee, "VBIST: An Integrated approach to On-Line/Off-Line BIST," Proc. Intl. Test Conf., pp. 910-917, 1998.
26. Kuppuswamy, R., et al., "Full Hold-Scan Systems in Microprocessors: Cost/Benefit. Analysis," Intel Technology Journal, Vol. 18, No. 1, Feb. 2004.
27. Kusko, M., et al., "99% AC Test Coverage Using Only LBIST on the 1-GHz IBM S/390 Z-series 900 Microprocessor," Proc. Intl. Test Conf., pp. 586-592, 2001.
28. Krantis, N., et al., "Effective Software Self-Test Methodology for Processor Cores," Proc. DATE, 2002.
29. Krantis, N., et al., "Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications," Proc. DATE, pp. 65-70, 2006.
30. Krstic, A., et al., "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design & Test of Computers, pp. 18-27, 2002.
31. McCluskey, E.J., "Verification Testing - A Pseudoexhaustive Test Technique," IEEE Trans. Computers, pp. 541-546, June 1984.
32. McCluskey, E.J., Logic Design Principles, Prentice Hall, 1986.
33. McNairy, C., and R. Bhatia, "Montecito: The Next Product in the Itanium Processor Family", Hot Chips 16, 2004.
34. Mitra, S., and K.S. Kim, "X-Compact: an efficient response compaction technique," IEEE Trans. CAD, pp. 421-432, 2004.
35. Molyneaux, R., et al., "Design-for-Testability Features of the Sun Microsystems Niagara2 CMP/CMT SPARC Chip", Intl. Test Conf, 2007.
36. "GeForce 7950 GPUs," http://www.nvidia.com/page/geforce_7950. html.
37. Parvathala, P., K. Maneparambil, and W. Lindsay, "FRITS: A Microprocessor Functional BIST Method," Proc. Intl. Test Conf., pp. 590-598, 2002.
38. Paschalis, A., and D. Gizopoulos, "Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors," IEEE Trans. CAD, pp. 88-99, Jan. 2005.
39. Saxena, J., et al., "An Analysis of Power Reduction Techniques in Scan Testing," Intl. Test Conf., p. 670-677, 2001.
40. Shen, J., and J.A. Abraham, "Native mode functional test generation for processors with applications to self test and design validation," Proc. Intl. Test Conf., pp. 18-23, 1998.
41. "OpenSPARC T1 Microarchitecture Specification," http://opensparc-t1.sunsource.net/specs/OpenSPARCT1_Micro_Arch. pdf.
42. "UltraSPARC T2 Processor," www.sun.com/processors/UltraSPARC- T2/datasheet.pdf.
43. TetraMAX ATPG User Guide, version Z-2007.03.
44. Touba, N. A., "Survey of Test Vector Compression Techniques," IEEE Design & Test of Computers, pp. 294-303, 2006.
45. Touba, N. A., and E. J. McCluskey, "Altering a Pseudo-Random Bit Sequence for Scan-Based BIST," Proc. Intl. Test Conf., pp. 167-175, 1996.
46. Weglarz, E., K. Saluja, and T.M. Mak, "Testing of Hard Faults in Simultaneous Multithreaded Processors," Proc. Intl. Symp. On-line Testing, pp. 95-100, 2004.
47. Wunderlich, H.J., and G. Kiefer, "Bit-Flipping BIST," Proc. ICCAD, pp. 337-343, 1996.
48. Whetsel, L., "Adapting Scan Architectures for Low Power Operation," Proc. Intl. Test Conf., pp. 863-872, 2000.
49. Yang, B., K. Wu, and R. Karri, "Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard," Proc. Intl. Test Conf., pp. 339-344, 2004.
50. Zyuban, V., and S. Kosonocky, "Low Power Integrated Scan Retention Mechanism," Intl. Symp. Low Power Design, pp. 98-102, 2002.