Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 4, 2007, Pages 743-751

  Paul, Bipul C ^a,b   Kang, Kunhyuk ^a,c   Kufluoglu, Haldun ^a,c   Alam, Muhammad A ^a,c   Roy, Kaushik ^a,c  

^a IEEE   (United States)

^b Toshiba America Research Inc   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Design for reliability; Negative bias temperature instability (nbti); Performance degradation; Threshold voltage degradation

Indexed keywords

DESIGN FOR RELIABILITY; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); PERFORMANCE DEGRADATION; THRESHOLD-VOLTAGE DEGRADATION;

INTEGRATED CIRCUITS; RELIABILITY; THERMAL EFFECTS;

COMPUTER AIDED DESIGN;

EID: 33947573759     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.884870     Document Type: Article

References (20)

1. N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, "Impact of bias temperature instability for direct tunneling ultrathin gate oxide on MOSFET scaling," in Proc. Symp. VLSI Technol. Tech. Dig. Papers, 1999, pp. 73-74.
2. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, "Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Lett., vol. 23, no. 12, pp. 734-736, Dec. 2002.
3. Y. H. Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman, and S. Hu, "Effect of pMOST bias-temperature instability on circuit reliability performance," in Proc. IEDM Tech. Dig., 2003, pp. 14.6.1-14.6.4.
4. D. Schroder and J. F. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, no. 1, pp. 1-18, 2003.
5. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs," in Proc. IEDM, 2003, pp. 346-349.
6. S. Zafar, B. H. Lee, and J. Stathis, "Evaluation of NBTI in HfO/sub 2/gate dielectric stacks with tungsten gates," IEEE Electron Device Lett., vol. 25, no. 3, pp. 153-155, Mar. 2004.
7. W. Abadeer and W. Ellis, "Behavior of NBTI under AC dynamic circuit conditions," in Proc. IRPS, 2003, pp. 17-22.
8. V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," in Proc. IRPS, 2002, pp. 248-253.
9. A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI impact on transistor and circuit: Models, mechanisms and scaling effects," in Proc. IEDM, 2003, pp. 14.5.1-14.5.4.
10. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, "Impact of NBTI on the temporal performance degradation of digital circuits," IEEE Electron Device Lett., vol. 26, no. 8, pp. 560-562, Aug. 2005.
11. C. P. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 7, pp. 1014-1025, Jul. 1999.
12. Device Group, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/ptm
13. M. A. Alam and S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microelectron. Reliab., vol. 45, no. 1, pp. 71-81, Jan. 2005.
14. M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. Hoboken, NJ: Wiley, 1993.
15. V. Reddy, J. Carulli, A. Krishnan, W. Bosch, and B. Burgess, "Impact of negative bias temperature instability on product parametric drift," in Proc. ITC, 2004, pp. 148-155.
16. Z. Chen, K. Roy, and T. Chou, "Power sensitivity - A new method to estimate power dissipation considering uncertain specifications of primary inputs," in Proc. ICCAD, 1997, pp. 40-44.
17. T. Sakurai and R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122-131, Feb. 1991.
18. S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. IRPS, 2004, pp. 273-282.
19. E. T. A. F. Jacobs and M. R. C. M. Berkelaar, "Gate sizing using statistical delay model," in Proc. DATE, 2000, pp. 283-290.
20. S. H. Choi, B. C. Paul, and K. Roy, "Novel sizing algorithm for yield improvement under process variation," in Proc. DAC, 2004, pp. 454-459.