-
1
-
-
84927710403
-
An O(N) Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs
-
February
-
A. U. Diril, Y. S. Dhillon, K. Choi, A. Chatterjee, "An O(N) Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs," ISVLSI, pp. 173-179, February 2003.
-
(2003)
ISVLSI
, pp. 173-179
-
-
Diril, A.U.1
Dhillon, Y.S.2
Choi, K.3
Chatterjee, A.4
-
2
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
-
April
-
T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, pp.584-594, April 1990.
-
(1990)
IEEE Journal of Solid-State Circuits
, vol.25
, pp. 584-594
-
-
Sakurai, T.1
Newton, A.R.2
-
3
-
-
0033699538
-
Run-time Voltage Hopping for Low Power Real-Time Systems
-
S. Lee, T. Sakurai, "Run-time Voltage Hopping for Low Power Real-Time Systems," DAC, pp.806-809, 2000.
-
(2000)
DAC
, pp. 806-809
-
-
Lee, S.1
Sakurai, T.2
-
4
-
-
0031639466
-
The Simulation and Evaluation of Dynamic Voltage Scheduling Algorithms
-
T. Pering, T. Burd, R. Brodersen, "The Simulation and Evaluation of Dynamic Voltage Scheduling Algorithms," ISLPED, pp.76-81, 1998.
-
(1998)
ISLPED
, pp. 76-81
-
-
Pering, T.1
Burd, T.2
Brodersen, R.3
-
5
-
-
0031342514
-
Energy Minimization Using Multiple Supply Voltages
-
December
-
J. Chang, M. Pedram, "Energy Minimization Using Multiple Supply Voltages," IEEE Trans. on VLSI Systems, vol.5, no.4, December 1997.
-
(1997)
IEEE Trans. on VLSI Systems
, vol.5
, Issue.4
-
-
Chang, J.1
Pedram, M.2
-
6
-
-
0030422286
-
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints
-
M. Johnson, K. Roy, "Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints," ICCD '96, pp.12 -77, 1996.
-
(1996)
ICCD '96
, pp. 12-77
-
-
Johnson, M.1
Roy, K.2
-
7
-
-
0035301566
-
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
-
April
-
P. Pant, R.K. Roy, A. Chattejee, "Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits," IEEE Trans. on VLSI Systems, vol.9, no.2, pp.390-394, April 2001.
-
(2001)
IEEE Trans. on VLSI Systems
, vol.9
, Issue.2
, pp. 390-394
-
-
Pant, P.1
Roy, R.K.2
Chattejee, A.3
-
8
-
-
0033359507
-
Low power synthesis of dual threshold voltage CMOS VLSI circuits
-
V. Sundararajan, K.K. Parhi, "Low power synthesis of dual threshold voltage CMOS VLSI circuits," ISLPED, pp.139-144, 1999.
-
(1999)
ISLPED
, pp. 139-144
-
-
Sundararajan, V.1
Parhi, K.K.2
-
9
-
-
0033899248
-
Dynamic back bias CMOS driver for low-voltage applications
-
Jan.
-
Y. Moisiadis, I. Bouras, A. Arapoyanni, "Dynamic back bias CMOS driver for low-voltage applications," Electronics Letters, vol.36, no.2, pp.135-136, Jan. 2000.
-
(2000)
Electronics Letters
, vol.36
, Issue.2
, pp. 135-136
-
-
Moisiadis, Y.1
Bouras, I.2
Arapoyanni, A.3
-
10
-
-
0034427485
-
A static power model for architects
-
J.A. Butts, G.S. Sohi, "A static power model for architects," IEEE/ACM MICRO, pp. 191-201, 2000.
-
(2000)
IEEE/ACM MICRO
, pp. 191-201
-
-
Butts, J.A.1
Sohi, G.S.2
-
11
-
-
0034259409
-
Analysis and future trend of short-circuit power
-
Sept.
-
K. Nose, T. Sakurai, "Analysis and future trend of short-circuit power," IEEE Trans. on CAD, vol.19, no.9, pp. 1023-1030, Sept. 2000.
-
(2000)
IEEE Trans. on CAD
, vol.19
, Issue.9
, pp. 1023-1030
-
-
Nose, K.1
Sakurai, T.2
-
12
-
-
84962272094
-
Leakage power estimation for deep submicron circuits in an ASIC design environment
-
R. Kumar, C.P. Ravikumar, "Leakage power estimation for deep submicron circuits in an ASIC design environment," DAC, pp.45-50, 2002.
-
(2002)
DAC
, pp. 45-50
-
-
Kumar, R.1
Ravikumar, C.P.2
-
13
-
-
0024716080
-
Generation of performance constraints for layout
-
Aug.
-
R. Nair, C.L. Berman, P.S. Hauge, E.J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. on CAD, vol.8, no.8, pp.860-874, Aug. 1989.
-
(1989)
IEEE Trans. on CAD
, vol.8
, Issue.8
, pp. 860-874
-
-
Nair, R.1
Berman, C.L.2
Hauge, P.S.3
Yoffa, E.J.4
-
14
-
-
84884698255
-
th for low-power and high-speed applications
-
th for low-power and high-speed applications," ASP-DAC, pp.469-474, 2000.
-
(2000)
ASP-DAC
, pp. 469-474
-
-
Nose, K.1
Sakurai, T.2
-
15
-
-
0346868117
-
An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages
-
R. Bai, S. Kulkami.W. Kwong, A. Srivastava, D. Sylvester, D.Blaauw, "An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages," ISVLSI, pp. 149-154, 2003.
-
(2003)
ISVLSI
, pp. 149-154
-
-
Bai, R.1
Kulkami, S.2
Kwong, W.3
Srivastava, A.4
Sylvester, D.5
Blaauw, D.6
-
16
-
-
0033100297
-
Design and optimization of dual-threshold circuits for low-voltage low-power applications
-
March
-
L. Wei, Z. Chen, K. Roy, M.C. Johnson, Y. Ye, V.K. De, "Design and optimization of dual-threshold circuits for low-voltage low-power applications," IEEE Trans. on VLSI Systems, pp. 16-24, vol.7, no.1, March 1999.
-
(1999)
IEEE Trans. on VLSI Systems
, vol.7
, Issue.1
, pp. 16-24
-
-
Wei, L.1
Chen, Z.2
Roy, K.3
Johnson, M.C.4
Ye, Y.5
De, V.K.6
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