Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 62-68

  Magklis, Grigorios ^a   Semeraro, Greg ^b   Albonesi, David H ^c,d   Dropsho, Steven G ^c   Dwarkadas, Sandhya ^c   Scott, Michael L ^c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b ROCHESTER INSTITUTE OF TECHNOLOGY   (United States)

^c University of Rochester   (United States)

^d UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SUPERSCALAR DATA; VOLTAGE SCALING;

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; COST EFFECTIVENESS; DATA PROCESSING; ELECTRIC FREQUENCY CONTROL; ELECTRIC POTENTIAL; ENERGY DISSIPATION;

MICROPROCESSOR CHIPS;

EID: 1342346135     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261388     Document Type: Review

References (10)

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