A clock power model to evaluate impact of architectural and technology optimizations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 844-855

  Duarte, David E ^a,b   Vijaykrishnan, N ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Clock power consumption modeling; Digital CMOS; Phase locked loop; VLSI low power design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; VLSI CIRCUITS;

CLOCK POWER MODEL;

ENERGY DISSIPATION;

EID: 0036999694     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808433     Document Type: Article

References (19)

1. P. E. Gronowski et al., "High performance microprocessor design," IEEE J. Solid-State Circuits, vol. 33, pp. 676-686, May 1998.
2. E. Friedman, "Clock distribution design in VLSI circuits: An overview," in Proc. IEEE ISCAS, 1994, pp. 1475-1478.
3. T.-H. Chao, Y.-C. Hsu, J.-M. Ho, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst. II, vol. 39, pp. 799-814, Nov. 1992.
4. S. Pullela, N. Menezes, and L. T. Pillage, "Low power IC clock tree design," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 263-266.
5. E. Tellez, A. Farrah, and M. Sarrafzadeh, "Activity-driven clock design for low power circuits," in Proc. ICCAD, 1995, pp. 62-65.
6. R. Chen, N. Vijaykrishnan, and M. J. Irwin, "Clock power issues in SOC designs," in Proc. IEEE VLSI Workshop, 1999, pp. 48-53.
7. D. Liu and C. Svensson, "Power consumption in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
8. D. Duarte, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir, "Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks," in Proc. Int. Conf. VLSI Design, 2001, pp. 248-253.
9. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural level power analysis and optimization," in Proc. IEEE ISCA, 2000, pp. 83-94.
10. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of simplepower: A cycle-accurate energy estimation tool," in Proc. DAC Conf., 2000, pp. 340-345.
11. J. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall Int., 1996, ch. 2 and 9.
12. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1994, pp. 180-191.
13. A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design. Boston, MA: Kluwer Academic, 1995, pp. 56-103.
14. A. Keshavarzi, K. Roy, and C. F. Hawkins, "Intrinsic leakage in low power deep submicron CMOS ICS," in Proc. Int. Test Conf., 1997, pp. 146-155.
15. D. Y. Jeong, G. Borríello, D. A. Hodges, and R. H. Katz, "Design of PLL-based clock generation circuits," IEEE J. Solid-State Circuits, vol. 22, pp. 255-261, Apr. 1987.
16. B. Tourette, "A 200 MHz, 600 μW CMOS PLL for mobile communication ASIC's," in Proc. IEEE ASIC Conf., 1999, pp. 366-369.
17. W. Ye and M. J. Irwin, "Power analysis of gated pipeline registers," in Proc. IEEE ASIC Conf., 1999, pp. 281-285.
18. P. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-799, May 2001.
19. D. Duarte, N. Vijaykrishnan, and M. J. Irwin "Impact of technology scaling in the clock system power," in Proc. IEEE Annu. Symp. VLSI (ISVLSI), Apr. 2002.