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Volumn 52, Issue 6, 2008, Pages 541-552

Is 3D chip technology the next growth engine for performance improvement?

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 61649087224     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2008.5388561     Document Type: Article
Times cited : (141)

References (36)
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    • Burns, J.A.1    Chen, C.K.2    Knect, J.M.3    Wyatt, P.W.4
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    • Crosstalk Attenuation with Ground Plane Structures in Three-Dimensionally Integrated Mixed Signal Systems
    • S. K. Kim, C. C. Liu, L. Xue, and S. Tiwari, "Crosstalk Attenuation with Ground Plane Structures in Three-Dimensionally Integrated Mixed Signal Systems," IEEE MTT-S International Microwave Symposium Digest, 2005, pp. 2155-2158.
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    • Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated with 65-nm Strained-Si/Low-k CMOS Technology
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.