3-D silicon integration and silicon packaging technology using silicon through-vias

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 8, 2006, Pages 1718-1724

  Knickerbocker, John U ^a,b   Patel, Chirag S ^b   Andry, Paul S ^b   Tsang, Cornelia K ^b   Buchwalter, L Paivikki ^b   Sprogis, Edmund J ^b   Gan, Hua ^b   Horton, Raymond R ^b   Polastre, Robert J ^b   Wright, Steven L ^b   Cotte, John M ^b  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

3 D; Chip integration; High bandwidth; Integrated decoupling capacitors; Interconnection; Silicon packaging; Silicon through vias

Indexed keywords

CHIP INTEGRATION; HIGH BANDWIDTH; INTEGRATED DECOUPLING CAPACITORS; INTERCONNECTION; SILICON PACKAGING; SILICON THROUGH-VIAS;

CAPACITORS; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; ELECTRONIC EQUIPMENT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; SURFACE MOUNT TECHNOLOGY;

SEMICONDUCTING SILICON;

EID: 33746875623     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.877252     Document Type: Conference Paper

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