Fine grain 3D integration for microarchitecture design through cube packing exploration

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 259-266

  Liu, Yongxiang ^a   Ma, Yuchun ^b   Kursun, Eren ^a   Reinman, Glenn ^a   Cong, Jason ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TSINGHUA UNIVERSITY   (China)

^c CALIFORNIA NANOSYSTEMS INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D DESIGN; COMPUTER DESIGNS; CUBE PACKING; FINE GRAINED; FLOOR-PLANNING; INSERTION TECHNIQUES; INTERCONNECT REDUCTION; INTERNATIONAL CONFERENCES; MICRO-ARCHITECTURE DESIGN; MULTI LAYERING; PEAK TEMPERATURES; PERFORMANCE IMPROVEMENTS; POWER DISSIPATIONS; SILICON LAYERS; SINGLE LAYERS;

ARCHITECTURAL DESIGN; DESIGN; NONMETALS; SILICON;

THREE DIMENSIONAL;

EID: 52949116040     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601911     Document Type: Conference Paper

References (32)

1. S. Das, A. Chandrakasan, and R. Reif. Design tools for 3-d integrated circuits. In. Proc. ASPDAC, pp. 53-56, January 2003.
2. K. Banerjee, S. Souri, P, Kapur, and K. Saraswat. 3-d ics: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. In In Proc. of IEEE, 89(5):602-633, May 2001.
3. B. Black, D. W. Nelson, C. Webb, and N. Samra. 3d processing technology and its impact on ia32 microprocessors. In Proc. Of ICCD, pp.316-318, 2004.
4. J. Cong, A. Jagannathan, Y. Ma, G. Reinman, J. Wei, and Y. Zhang. An automated design flow for 3d microarchitecture evaluation. In Proc. Asia and South Paci_c Design Automation Conf, January 2006.
5. J. Cong, J.Wei, and Y. Zhang. A Thermal-Driven Floorplanning Algorithm for 3D ICs, Proc. IEEE ICCAD, 2004.
6. K. Skadron, MR Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-Aware Microarchitecture. In Proceedings of the 30th ISCA, pp. 2-13, San Diego, CA, June 2003.
7. H. Yamazaki, K. Sakanusm, S. Nakatake, Y. Kajitani, "The 3D-Packing by Meta Data Structure and Packing Heuristics", IEICE Trans. Fundamentals, Vol.E83-A, No.4 2000.
8. P.H. Yuh, C.-L. Yang, Y.-W. Chang, H.-L. Chen, "Temporal Floorplanning Using 3D-subTCG", Proc. ASPDAC, pp.723-728, 2004
9. Y. Tsai, Y. Xie, N. Vijaykrishnan, and M. Irwin. Three-dimensional cache design exploration using 3dcacti. In International Conference on Computer Design, October 2005.
10. S. Das, A. Chandrakasan, and R. Reif. Design tools for 3-d integrated circuits. In Proc. ASPDAC, pp. 53-56, January 2003.
11. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th Annual International Symposium on Computer Architecture, pages 206ñ21.8, June 1997.
12. G. Reinman and N. Jouppi. Cacti 2.0: An integrated cache timing and power model. In Technical Report, 2000.
13. R.Ronnen, A.Mendelson, K.Lai, S-L Liu, F.Pollack, and J.P.Shen. Coming challenges in microarchitecture and architecture. In Proceedings of the IEEE, Vol. 89, No.3, pages 325ñ340, 2001.
14. M. B. Kleiner, S. A. Kuhn, P. Ramm, and W. Weber. Performance and Improvement of the Memory Hierarchy of Rise-Systems by Application of 3-D Technology, IEEE Trans. Comp. Packag, Manufact. Technol. B, 19, 1996.
15. http://www.irvine-sensors.com/r_and_d.html#high
16. Y. K. Tsui, S. W. R. Lee, J. S. Wu, J. K. Kim, and M. M. F Yuen. Three-Dimensional Packaging for Multi-chip Module with Through-the-Silicon Via Hole, Electronics Packaging Technology, 5th Conference, pp. 1-7, 2003.
17. G. McFarland and M. Flynn. Limits of scaling mosfets. CSL TR-95-62, Stanford University, November 1995.
18. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New paradigm of predictive mosfet and interconnect modeling for early circuit design. In Proc. of Custom Integrated Circuit Conference, 2000.
19. A. Jagannathan, H. H. Yang, K. Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, and Jason Cong. Microarchitecture Evaluation with Floorplanning and Interconnect Pipelining, Proc. of the Asia Pacific Design Automation Conference, 2005.
20. J. Cong and D. Z. Pan. Interconnect Estimation And Planning For Deep Submicron Designs. Proceedings of the 36th ACM/IEEE Conference on Design Automation, pp. 507-510, 1999.
21. E. Sprangle and D. Carmean. Increasing Processor Performance by Implementing Deeper Pipelines, ISCA. '02: Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 25-34, 2002.
22. Y. Xie, G. H. Loh, B. Black, K. Bernstein. Design Space Exploration for 3D Architectures. ACM Journal, of Emerging Technologies in Computing Systems, 2(2):65-103, April 2006.
23. H. Xianlong, H. Gang et al. "Corner Block List: An Effective and Efficient Topological. Representation of Non-slicing Floorplan" ICCAD'2000.
24. P.Wilkerson, A.Raman, and M.Turowski. Fast, automated thermal simulation for three-dimensional integrated circuits. In Conference on Thermal and Thermomechanical Phenomena in Electronic Circuits, Itherm, 2004.
25. Y. Ma, X. Hong, and C.K. Cheng S. Dong. 3D CBL: An efficient algorithm for general 3-dimensional packisng problems. In IEEE International Midwest Symposium on Circuits and Systems, 2005.
26. D.C. Burger and T. M. Austin. The SimpleScalar Tool Set, Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
27. J.Cong and Y.Zang. Thermal-driven multilevel routing for 3-d ics. In Asia Pacific Design Automation Conference, pages 121-126, 2005.
28. K. Puttaswamy and G. H. Loh, "Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor," ACM/IEEE Great Lakes Symposium on VLSI, 19-24, 2006.
29. B.Black, M.Annavaram, N.Brekelbaum, J.Devale, L.Jiang, G.H.Loh, D.McCauley, P.Morrow, D.W.Nelson, D.Pantuso, P.Reed, J.Rupley, S.Shankar, J.Shen, C.Webb, Die Stacking (3D) Microarchitecture International Symposium on Microarchitecture 2006
30. K. Puttaswamy, G. H. Loh Dynamic Instruction Schedulers in a 3-Dimensional Integration Technology In the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 153-158, May 1, 2006, USA.
31. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng. Integrating Dynamic Thermal Via Planning With 3D Floorplanning Algorithm. ACM International Symposium on Physical Design. 2006: 178-185
32. Jason Cong, Eren Kursun, Yongxiang Liu, Yuchun Ma and Glenn Reinman. 3D Architecture Modeling and Exploration, UCLA Computer Science Technical Report UCLA/CSD-060032, January 2006