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Volumn , Issue , 2005, Pages 76-82
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CMOS transistor processing compatible with monolithic 3-D integration
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS TRANSISTORS;
DEPOSITION PROCESS;
DOPANT ACTIVATION;
ELECTRICAL ACTIVATION;
HEATING MATERIALS;
HIGH TEMPERATURE;
LOW-TEMPERATURE OXIDES;
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS;
ANNEALING;
CHEMICAL ACTIVATION;
CMOS INTEGRATED CIRCUITS;
DOPING (ADDITIVES);
THREE DIMENSIONAL;
TRANSISTORS;
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EID: 33947376744
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (9)
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