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Volumn 2005, Issue , 2005, Pages 2155-2158

Crosstalk attenuation with ground plane structures in Three-dimensionally integrated mixed signal systems

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; COMPUTER SIMULATION; INTEGRATED CIRCUITS; METALLIZING; MOS DEVICES; SIGNAL PROCESSING; TRANSISTORS;

EID: 33749248360     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2005.1517176     Document Type: Conference Paper
Times cited : (11)

References (13)
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  • 2
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  • 3
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    • Three-dimensional metal gate-high k-GOI CMOSFETs on 1-poly-6-metal 0.18 μm Si device
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    • D. S. Yu et al., "Three-dimensional metal gate-high k-GOI CMOSFETs on 1-poly-6-metal 0.18 μm Si device," IEEE IEEE Electron Device Lett., vol. 26, pp. 118-120, Feb. 2005.
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    • Yu, D.S.1
  • 4
    • 33750928184 scopus 로고    scopus 로고
    • 3-D heterogeneous ICs: A technology for the next decade and beyond
    • K. Banerjee et al., "3-D heterogeneous ICs: a technology for the next decade and beyond," Proc. IEEE, vol. 89, pp. 602-633, 2001.
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    • Banerjee, K.1
  • 5
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    • 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
    • Feb.
    • J. Burns et al., "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 268-269, Feb. 2001.
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    • Burns, J.1
  • 6
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    • Mar.
    • L. Xue et al., "Three-dimensional integration: technology, use, and issues for mixed-signal applications," IEEE Trans. Electron Devices, vol. 50, pp. 601-609, Mar. 2003.
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    • Xue, L.1
  • 7
    • 0036928172 scopus 로고    scopus 로고
    • Electrical integrity of the state-of-the-art.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
    • K. W. Guarini, et al., "Electrical integrity of the state-of-the-art .13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication," IEDM Tech. Dig., pp. 943, 2002
    • (2002) IEDM Tech. Dig. , pp. 943
    • Guarini, K.W.1
  • 8
    • 16244416502 scopus 로고    scopus 로고
    • Low temperature silicon circuit layering for three-dimensional integration
    • Oct.
    • S. K. Kim et al., "Low temperature silicon circuit layering for three-dimensional integration," Proc. IEEE Int. SOI Conf., pp. 136-138, Oct. 2004.
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  • 9
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    • Effective crosstalk isolation through p+ Si substrate with semi-insulation porous Si
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    • H.-S. Kim et al., "Effective crosstalk isolation through p+ Si substrate with semi-insulation porous Si," IEEE Electron Device Lett., vol. 23, pp. 160-162, Mar. 2002.
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  • 10
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  • 11
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  • 12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.