A 65nm 2-billion-transistor quad-core Itanium® processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 91-93

  Stackhouse, Blaine ^a   Cherkauer, Brian ^a   Gowan, Mike ^b   Gronowski, Paul ^a   Lyles, Chris ^a  

^a INTEL CORPORATION   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

65NM CMOS; DUAL-THREADED CORES; HIGH-SPEED LINKS; ITANIUM; MEMORY BANDWIDTHS; SYSTEM INTERFACES;

BANDWIDTH;

EID: 49549122471     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523072     Document Type: Conference Paper

References (3)

1. S. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, et al., "The Implementation of the Itanium 2 Microprocessor", IEEE J. of Solid State Circuits, vol. 37, no. 11, pp. 1448-1460, Nov. 2002.
2. S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, et al., "The Implementation of a 2-Core, Multi-Threaded Itanium⊙ Family Microprocessor", IEEE J. of Solid State Circuits, vol. 41, no. 1, pp. 197-209, Jan. 2006.
3. D. Krueger, E. Francom, J. Langsdorf, "Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium⊙ Family Processor", ISSCC Dig. Tech. Papers, pp. 94-95, Feb. 2008.