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Volumn 1, Issue , 2001, Pages 40-45

The potential and realization of multi-layers three-dimensional integrated circuit

Author keywords

3 D Integrated Circuits; recrystallization; Stacked Transistors; Thin Film Transistors; Wafer Bonding

Indexed keywords


EID: 84966565037     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2001.981421     Document Type: Conference Paper
Times cited : (7)

References (14)
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  • 7
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    • V. Subramanian, M. Toita, N. R. Ibrahim, S. J. Souri, and K. C. Saraswat, "Low-Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFT's for Vertical Integration Applications", IEEE EDL, vol. 20, no. 7, p. 341-3, 1999
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    • Lee, S.-W.1    Joo, S.-K.2
  • 10
    • 0033342070 scopus 로고    scopus 로고
    • Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization
    • S. Jagar, M. Chan, M.C. Poon, H. Wang, M. Qin, P. K. Ko, and Y. Wang, "Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization", 1999 IEDM Tech. Dig, pp. 293-296
    • 1999 IEDM Tech. Dig , pp. 293-296
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  • 12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.