-
1
-
-
0034841272
-
A practical methodology for early buffer and wire resource allocation
-
C. J. Alpert, J. H. Hu, S. S. Sapatnekar, and P. G. Villarrubia, "A practical methodology for early buffer and wire resource allocation," Proc. of DAC, pp. 189-194, 2001.
-
(2001)
Proc. of DAC
, pp. 189-194
-
-
Alpert, C.J.1
Hu, J.H.2
Sapatnekar, S.S.3
Villarrubia, P.G.4
-
2
-
-
0032138427
-
Multilevel circuit partitioning
-
August
-
C. J. Alpert, J.-H. Huang, and A. B. Kahng, "Multilevel circuit partitioning," IEEE Trans. CAD, vol. 17, no. 8, pp. 655-667, August 1998.
-
(1998)
IEEE Trans. CAD
, vol.17
, Issue.8
, pp. 655-667
-
-
Alpert, C.J.1
Huang, J.-H.2
Kahng, A.B.3
-
4
-
-
0034477815
-
Multilevel optimization for large-scale circuit placement
-
T. F. Chan, J. Cong, T. Kong, J. R. Shinnerl, "Multilevel optimization for large-scale circuit placement," Proc. of ICCAD, pp. 171-176, 2000.
-
(2000)
Proc. of ICCAD
, pp. 171-176
-
-
Chan, T.F.1
Cong, J.2
Kong, T.3
Shinnerl, J.R.4
-
5
-
-
0033701594
-
B*-trees: A new representation for non-slicing floorplans
-
Y.-C. Chang, Y.-W. Chang, G.-M. Wu and S.-W. Wu, "B*-trees: A new representation for non-slicing floorplans," Proc. of DAC, pp. 458-463, 2000.
-
(2000)
Proc. of DAC
, pp. 458-463
-
-
Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
-
6
-
-
0035212842
-
Multilevel approach to full-chip gridless routing
-
J. Cong, J. Fang, and Y. Zhang, "Multilevel approach to full-chip gridless routing," Proc. of ICCAD, pp. 396-403, 2001.
-
(2001)
Proc. of ICCAD
, pp. 396-403
-
-
Cong, J.1
Fang, J.2
Zhang, Y.3
-
7
-
-
0033338004
-
Buffer block planning for interconnect-driven floorplanning
-
J. Cong, T. Kong and D. Z. Pan, "Buffer Block Planning for Interconnect-Driven Floorplanning," Proc. of ICCAD, pp. 358-363, 1999.
-
(1999)
Proc. of ICCAD
, pp. 358-363
-
-
Cong, J.1
Kong, T.2
Pan, D.Z.3
-
8
-
-
0036907173
-
An enhanced multilevel routing system
-
J. Cong, M. Xie, and Y. Zhang, "An enhanced multilevel routing system," Proc. Of ICCAD, pp. 51-58, 2002.
-
(2002)
Proc. Of ICCAD
, pp. 51-58
-
-
Cong, J.1
Xie, M.2
Zhang, Y.3
-
9
-
-
0032690067
-
An O-tree representation of non-slicing floorplan and its applications
-
P.-N. Guo, C.-K. Cheng, and T. Yoshimura, "An O-tree representation of non-slicing floorplan and its applications," Proc. of DAC, pp. 268-273, 1999.
-
(1999)
Proc. of DAC
, pp. 268-273
-
-
Guo, P.-N.1
Cheng, C.-K.2
Yoshimura, T.3
-
11
-
-
0042192063
-
Simultaneous floorplanning and buffer block planning
-
H.-R. Jiang, Y-W, Chang, J.-Y. Jou, and K.-Y. Chao, "Simultaneous floorplanning and buffer block planning," Proc. of ASP-DAC, pp. 431-434, 2003.
-
(2003)
Proc. of ASP-DAC
, pp. 431-434
-
-
Jiang, H.-R.1
Chang, Y.-W.2
Jou, J.-Y.3
Chao, K.-Y.4
-
12
-
-
0032681035
-
Multilevel k-way hypergraph partitioning
-
G. Karypis and V. Kumar, "Multilevel k-way hypergraph partitioning," Proc. of DAC, pp. 343-348, 1999.
-
(1999)
Proc. of DAC
, pp. 343-348
-
-
Karypis, G.1
Kumar, V.2
-
13
-
-
0042693220
-
Noise-aware buffer planning for interconnect-driven floorplanning
-
S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, "Noise-aware buffer planning for interconnect-driven floorplanning," Proc. of ASP-DAC, pp. 423-426, 2003.
-
(2003)
Proc. of ASP-DAC
, pp. 423-426
-
-
Li, S.-M.1
Cherng, Y.-H.2
Chang, Y.-W.3
-
14
-
-
0034855935
-
TCG: A transitive closuer graph based representation for non-slicing floorplans
-
J.-M. Lin and Y.-W. Chang, "TCG: A transitive closuer graph based representation for non-slicing floorplans," Proc. of DAC, pp. 764-769, 2001.
-
(2001)
Proc. of DAC
, pp. 764-769
-
-
Lin, J.-M.1
Chang, Y.-W.2
-
15
-
-
0036051250
-
TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans
-
J.-M. Lin and Y.-W. Chang, "TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans," Proc. of DAC, pp. 842-847, 2002.
-
(2002)
Proc. of DAC
, pp. 842-847
-
-
Lin, J.-M.1
Chang, Y.-W.2
-
16
-
-
0141750617
-
Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme
-
J.-M. Lin, Y.-W. Chang, and S.-P. Lin, "Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme," IEEE Trans. VLSI Systems, 2003.
-
(2003)
IEEE Trans. VLSI Systems
-
-
Lin, J.-M.1
Chang, Y.-W.2
Lin, S.-P.3
-
17
-
-
0036907026
-
A novel framework for multilevel routing considering routability and performance
-
S.-P. Lin and Y.-W. Chang, "A novel framework for multilevel routing considering routability and performance," Proc. of ICCAD, pp. 44-50, 2002.
-
(2002)
Proc. of ICCAD
, pp. 44-50
-
-
Lin, S.-P.1
Chang, Y.-W.2
-
18
-
-
0029488327
-
Rectangle-packing based module placement
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-packing based module placement," Proc. of ICCAD, pp. 472-479, 1995.
-
(1995)
Proc. of ICCAD
, pp. 472-479
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
19
-
-
0030408582
-
Module placement on BSG-structure and IC layout applications
-
S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module placement on BSG-structure and IC layout applications," Proc. of ICCAD, pp. 484-491, 1996.
-
(1996)
Proc. of ICCAD
, pp. 484-491
-
-
Nakatake, S.1
Fujiyoshi, K.2
Murata, H.3
Kajitani, Y.4
-
20
-
-
85031277343
-
Automatic floorplan design
-
R. H. J. M. Otten, "Automatic floorplan design," Proc. of DAC, pp. 261-267, 1982.
-
(1982)
Proc. of DAC
, pp. 261-267
-
-
Otten, R.H.J.M.1
-
21
-
-
0033723975
-
Routability-driven repeater block planning for interconnect-centric floorplanning
-
P. Sarkar, V. Sundararaman and C.K. Koh, "Routability-driven repeater block planning for interconnect-centric floorplanning," Proc. of ISPD, 2000.
-
(2000)
Proc. of ISPD
-
-
Sarkar, P.1
Sundararaman, V.2
Koh, C.K.3
-
22
-
-
85040657895
-
A new algorithm for floorplan design
-
D. F. Wong and C. L. Liu, "A new algorithm for floorplan design," Proc. of DAC, pp. 101-107, 1986.
-
(1986)
Proc. of DAC
, pp. 101-107
-
-
Wong, D.F.1
Liu, C.L.2
-
23
-
-
0033691295
-
Floorplan area minimization using Lagrangian relaxation
-
F.Y. Young, C. C.N. Chu, W.S. Luk, and Y.C. Wong, "Floorplan area minimization using Lagrangian relaxation," Proc. of ISPD., pp. 174-179, 2000.
-
(2000)
Proc. of ISPD
, pp. 174-179
-
-
Young, F.Y.1
Chu, C.C.N.2
Luk, W.S.3
Wong, Y.C.4
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